Latency Insensitive Protocols have been proposed as a viable mean to speed up large
Systems-on-Chip where the limit in clock frequency is given by long global wires connecting …

Extracting maximum performance of multi-core architectures is a difficult task primarily due to
bandwidth limitations of the memory subsystem and its complex hierarchy. In this work, we …

The requirements placed on computer architectures from modern computational workloads
have driven constant performance improvements. In the last 15 years, the largest source of …

Poor scalability on parallel architectures can be attributed to several factors, among which
idle times, data movement, and runtime overhead are predominant. Conventional parallel …

Tapas is our new C++ programming framework for hierarchical algorithms such as N-body,
on large scale heterogeneous supercomputers. Although N-body and their variants are …

Computational science is at the core of many scientific domains as much in academic
research than in industrial research and development. Computer simulations are used in a …

For many years, the stability of the architecture paradigm has facilitated the performance
portability of large HPC codes from one generation of supercomputers to another. The …

Tapas is our new C++ programming framework for hierarchical algorithms such as n-body,
on large scale heterogeneous supercomputers. Although n-body and their variants are …