(57) Operating a scan chain of a test circuit of an integrated circuit to have either a single
fanout or multiple fanout to a compres sor. The test circuit receives a fanout control signal for …

The present invention relates to test architectures for inte grated circuits, and in particular to
test architectures that allows changing values on the scan configuration signals during the …

Scachai Nagative egative output from the first and second sets of state variable devices,
respectively. The compressors also generate first and second compressor output data …

A semiconductor integrated circuit equipped with multiple serially coupled scan chains
which are used to shift inspection data based on different clock signals in order to inspect a …

A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This
test architecture advantageously allows for changing scan inputs during the scan operation …

Scan-based testing includes replacing state variable devices that make up sequential
circuits with pseudo inputs and outputs. Values of the pseudo inputs and outputs can be set …

An integrated circuit (IC) that is operable in scan test and functional modes includes Scan-in
pads, Scan-out pads, Scan chains, a compressor, a decompressor, a test control register …

GOIR 3L/385(2006.01) GOIR 3L/383(2006.01)(57) ABSTRACT GOIR 3L/38(2006.01) A
method for localizing at least one scan flop associated with GOIR 3L/39(2006.01) a fault in …

(57) ABSTRACT A system and method for determining a relative importance of a selected
test in a plurality of tests, comprising a computational device for receiving one or more …

A core circuit that can be connected in a hierarchical manner, and configured to test a
multiple circuits is disclosed. The core circuit includes at least one real input for receiving …