High-speed black phosphorus field-effect transistors approaching ballistic limit

X Li, Z Yu, X Xiong, T Li, T Gao, R Wang, R Huang… - Science …, 2019 - science.org
As a strong candidate for future electronics, atomically thin black phosphorus (BP) has
attracted great attention in recent years because of its tunable bandgap and high carrier …

Analysis of self-heating effects in ultrathin-body SOI MOSFETs by device simulation

C Fiegna, Y Yang, E Sangiorgi… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS
technology and applies device simulation to analyze the impact of thermal effects on the …

Understanding quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drain

P Palestri, D Esseni, S Eminente… - … on Electron Devices, 2005 - ieeexplore.ieee.org
In this paper, and in Part II, Monte Carlo (MC) simulations including quantum corrections to
the potential and calibrated scattering models are used to study electronic transport in bulk …

Theoretical study of some physical aspects of electronic transport in nMOSFETs at the 10-nm gate-length

MV Fischetti, TP O'Regan, S Narayanan… - … on Electron Devices, 2007 - ieeexplore.ieee.org
We discuss selected aspects of the physics of electronic transport in nMOSFETs at the 10-
nm scale: Long-range Coulomb interactions, which may degrade performance and even …

Investigation of the transport properties of silicon nanowires using deterministic and Monte Carlo approaches to the solution of the Boltzmann transport equation

M Lenzi, P Palestri, E Gnani, S Reggiani… - … on Electron Devices, 2008 - ieeexplore.ieee.org
We investigate the transport properties of silicon-nanowire FETs by using two different
approaches to the solution of the Boltzmann equation for the quasi-1-D electron gas …

Scaling MOSFETs to 10 nm: Coulomb effects, source starvation, and virtual source model

MV Fischetti, S Jin, TW Tang, P Asbeck, Y Taur… - Journal of computational …, 2009 - Springer
In our attempts to scale FETs to the 10 nm length, alternatives to conventional Si CMOS are
sought on the grounds that:(1) Si seems to have reached its technological and performance …

Multisubband Monte Carlo study of transport, quantization, and electron-gas degeneration in ultrathin SOI n-MOSFETs

L Lucci, P Palestri, D Esseni… - IEEE transactions on …, 2007 - ieeexplore.ieee.org
This paper presents a new self-consistent multisubband Monte Carlo model for electronic
transport in the inversion layer of decananometric MOSFETs. The simulator is 2-D in real …

On backscattering and mobility in nanoscale silicon MOSFETs

C Jeong, DA Antoniadis… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
The DC current-voltage characteristics of an n-channel silicon MOSFET with an effective
gate length of about 60 nm are analyzed and interpreted in terms of scattering theory. The …

Highly manufacturable double-gate FinFET with gate-source/drain underlap

JW Yang, PM Zeitzoff, HH Tseng - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
The speed performance of a double-gate (DG) FinFET CMOS with gate-source/drain (GS/D)
underlap is investigated using 2-D device and mixed-mode circuit simulation. By optimizing …

Simulation of self-heating effects in different SOI MOS architectures

M Braccioli, G Curatola, Y Yang, E Sangiorgi… - Solid-state …, 2009 - Elsevier
This paper discusses self-heating effects in different silicon-on-insulator architectures by 3D
electro-thermal simulations. First of all, we compare different device architectures such as …