Machine learning for electronic design automation: A survey

G Huang, J Hu, Y He, J Liu, M Ma, Z Shen… - ACM Transactions on …, 2021 - dl.acm.org
With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

MLCAD: A survey of research in machine learning for CAD keynote paper

M Rapp, H Amrouch, Y Lin, B Yu… - … on Computer-Aided …, 2021 - ieeexplore.ieee.org
Due to the increasing size of integrated circuits (ICs), their design and optimization phases
(ie, computer-aided design, CAD) grow increasingly complex. At design time, a large design …

A survey of machine learning for computer architecture and systems

N Wu, Y Xie - ACM Computing Surveys (CSUR), 2022 - dl.acm.org
It has been a long time that computer architecture and systems are optimized for efficient
execution of machine learning (ML) models. Now, it is time to reconsider the relationship …

IronMan-Pro: Multiobjective design space exploration in HLS via reinforcement learning and graph neural network-based modeling

N Wu, Y Xie, C Hao - … on Computer-Aided Design of Integrated …, 2022 - ieeexplore.ieee.org
Despite the great success of high-level synthesis (HLS) tools, we observe several
unresolved challenges: 1) the high-level abstraction of HLS programming styles sometimes …

A survey of graph neural networks for electronic design automation

DS Lopera, L Servadei, GN Kiprit… - 2021 ACM/IEEE 3rd …, 2021 - ieeexplore.ieee.org
Driven by Moore's law, the chip design complexity is steadily increasing. Electronic Design
Automation (EDA) has been able to cope with the challenging very large-scale integration …

Towards a comprehensive benchmark for high-level synthesis targeted to FPGAs

Y Bai, A Sohrabizadeh, Z Qin, Z Hu… - Advances in Neural …, 2023 - proceedings.neurips.cc
High-level synthesis (HLS) aims to raise the abstraction layer in hardware design, enabling
the design of domain-specific accelerators (DSAs) like field-programmable gate arrays …

Programming and synthesis for software-defined FPGA acceleration: status and future prospects

YH Lai, E Ustun, S Xiang, Z Fang, H Rong… - ACM Transactions on …, 2021 - dl.acm.org
FPGA-based accelerators are increasingly popular across a broad range of applications,
because they offer massive parallelism, high energy efficiency, and great flexibility for …

High-level synthesis performance prediction using gnns: Benchmarking, modeling, and advancing

N Wu, H Yang, Y Xie, P Li, C Hao - Proceedings of the 59th ACM/IEEE …, 2022 - dl.acm.org
Agile hardware development requires fast and accurate circuit quality evaluation from early
design stages. Existing work of high-level synthesis (HLS) performance prediction usually …

A comprehensive survey on electronic design automation and graph neural networks: Theory and applications

D Sánchez, L Servadei, GN Kiprit, R Wille… - ACM Transactions on …, 2023 - dl.acm.org
Driven by Moore's law, the chip design complexity is steadily increasing. Electronic Design
Automation (EDA) has been able to cope with the challenging very large-scale integration …

High-level synthesis hardware design for fpga-based accelerators: Models, methodologies, and frameworks

RS Molina, V Gil-Costa, ML Crespo, G Ramponi - IEEE Access, 2022 - ieeexplore.ieee.org
Hardware accelerators based on field programmable gate array (FPGA) and system on chip
(SoC) devices have gained attention in recent years. One of the main reasons is that these …