A Hierarchical Adaptive Multi-Task Reinforcement Learning Framework for Multiplier Circuit Design

[PDF] openreview.net

Reinforcement Learning within Tree Search for Fast Macro Placement

Z Geng, J Wang, Z Liu, S Xu, Z Tang… - … on Machine Learning, 2024 - openreview.net
Macro placement is a crucial step in modern chip design, and reinforcement learning (RL)
has recently emerged as a promising technique for improving the placement quality …
被引用次数：2 相关文章
[PDF] arxiv.org

Benchmarking end-to-end performance of ai-based chip placement algorithms

Z Wang, Z Geng, Z Tu, J Wang, Y Qian, Z Xu… - arXiv preprint arXiv …, 2024 - arxiv.org
The increasing complexity of modern very-large-scale integration (VLSI) design highlights
the significance of Electronic Design Automation (EDA) technologies. Chip placement is a …
被引用次数：2 相关文章 所有 2 个版本
[PDF] arxiv.org

SeaDAG: Semi-autoregressive Diffusion for Conditional Directed Acyclic Graph Generation

X Zhou, X Li, Y Lian, Y Wang, L Chen, M Yuan… - arXiv preprint arXiv …, 2024 - arxiv.org
We introduce SeaDAG, a semi-autoregressive diffusion model for conditional generation of
Directed Acyclic Graphs (DAGs). Considering their inherent layer-wise structure, we …
相关文章 所有 2 个版本
[PDF] arxiv.org

RTLRewriter: Methodologies for Large Models aided RTL Code Optimization

X Yao, Y Wang, X Li, Y Lian, R Chen, L Chen… - arXiv preprint arXiv …, 2024 - arxiv.org
Register Transfer Level (RTL) code optimization is crucial for enhancing the efficiency and
performance of digital circuits during early synthesis stages. Currently, optimization relies …
相关文章 所有 2 个版本