Optimization of thermal aware multilevel routing for 3D IC
P Sivakumar, K Pandiaraj, K JeyaPrakash - Analog Integrated Circuits and …, 2020 - Springer
Due to the technological advancements, the three dimensional Integrated Circuits become
the most popular technology. But it has the major drawback of increased time consumption …
the most popular technology. But it has the major drawback of increased time consumption …
An efficient partitioning and placement based fault TSV detection in 3D-IC using deep learning approach
RK Radhakrishnan Nair, S Pothiraj… - Journal of Ambient …, 2021 - Springer
Over topical eras, three dimensional Integrated Circuit (3D-IC) fabrications have become
vital among the researchers and industrial people, owing to its wide range of amenities …
vital among the researchers and industrial people, owing to its wide range of amenities …
TSV aware 3D IC partitioning with area optimization
JP Kadambarajan, S Pothiraj - Arabian Journal for Science and …, 2021 - Springer
A paradigm shift has been witnessed in microelectronic industry in recent days with more
and more research works focusing on transformation of Integrated Circuits from 2 to 3D …
and more research works focusing on transformation of Integrated Circuits from 2 to 3D …
Cluster-aware allocation of spare TSVs for enhanced reliability in 3D ICs
Abstract Three-dimensional Integrated-Circuits (3D ICs) based on Through-Silicon-Via
(TSV) technology offer numerous advantages, including high density, enhanced bandwidth …
(TSV) technology offer numerous advantages, including high density, enhanced bandwidth …
A cost-effective repair scheme for clustered TSV defects in 3D ICs
The current industry trend favors TSV (Through-Silicon-Via) based 3D ICs (Three-
dimensional Integrated-Circuits) due to their several benefits. However, the complex …
dimensional Integrated-Circuits) due to their several benefits. However, the complex …
TSV-Cluster defect tolerance using tree-based redundancy for yield improvement of 3-D ICs
Through silicon via (TSV)-based 3-D integrated circuit (3-D IC) has several advantages like
high density, high bandwidth, and low-power consumption. However, many defects in TSV …
high density, high bandwidth, and low-power consumption. However, many defects in TSV …
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs
Abstract The adoption of Through-Silicon-Vias (TSVs) in Three-Dimensional Integrated
Circuits (3D ICs) is gaining momentum in the industry, thanks to the numerous advantages it …
Circuits (3D ICs) is gaining momentum in the industry, thanks to the numerous advantages it …
Instant Test and Repair for TSVs using Differential Signaling
CY Wen, SY Huang - Journal of Electronic Testing, 2024 - Springer
Abstract A faulty Through Silicon Via (TSV) could spoil a 3D IC and cause hefty loss as the
potentially expensive known-good-dies bonded together must be discarded. This work …
potentially expensive known-good-dies bonded together must be discarded. This work …
A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs
Y Ge, TS Sandhu, D Truhachev… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Existing methods used for the clock distribution of multiple dies employ a balanced tree
structure to minimize the impact of the within-die process and loading variations. No …
structure to minimize the impact of the within-die process and loading variations. No …
Virtualization-based efficient TSV repair for 3-D integrated circuits
M Imran, H Han, J Kim, T Kwon, J Chung… - IEEE Access, 2019 - ieeexplore.ieee.org
Three-dimensional (3-D) integration offers a promising solution to the technology scaling
barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of …
barriers. Reliability of the 3-D Integrated Circuits (ICs) is highly dependent on the integrity of …