[图书][B] MOSFET modeling for circuit analysis and design

C Galup-Montoro - 2007 - books.google.com
This is the first book dedicated to the next generation of MOSFET models. Addressed to
circuit designers with an in-depth treatment that appeals to device specialists, the book …

Silicon devices and process integration

B El-Kareh - New York: Springer. doi, 2009 - Springer
State-of-the-art silicon devices and integrated process technologies are covered in this
book. The eight chapters represent a comprehensive discussion of modern silicon devices …

An Investigation of Process Variations and Mismatch Characteristics of Vertical Bipolar Junction Transistors

X Liu, Z Yang - IEEE Access, 2023 - ieeexplore.ieee.org
Bipolar junction transistors (BJT) are widely used integrated devices for analog circuits. For
most of analog applications, the process variation and the match performance of BJT pairs …

Analysis and modeling of current mismatch in negative capacitance field-effect transistor

R Goel, A Sharma, YS Chahuan - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this work, we analyze the impact of random dopant fluctuations (RDFs) on the mismatch
behavior of the negative capacitance field-effect transistor (NCFET). We observe that the …

Comprehensive matching characterization of analog CMOS circuits

H Masuda, T Kida, S Ohkawa - IEICE Transactions on …, 2009 - search.ieice.org
A new analog mismatch model in circuit level has been developed. MOS transistor's small
signal parameters are modeled in term of their matching character for both strong-and weak …

A computer-aided approach for voltage reference circuit design

F Olivera, A Petraglia - Analog Integrated Circuits and Signal Processing, 2016 - Springer
This work presents a computer-aided design (CAD) approach for voltage reference circuits
by controlling main characteristics, such as temperature coefficient, power consumption …

Modelo do descasamento (mismatch) entre transistores MOS

HD Klimach - 2008 - lume.ufrgs.br
Diversos modelos teóricos para o descasamento entre dispositivos na tecnologia MOS
foram propostos desde a década de'80, sendo que geralmente estes pecam ou pela …

Analysis and design of a robust floating point cmos image sensor

J Rhee, D Park, Y Joo - IEEE Sensors Journal, 2009 - ieeexplore.ieee.org
A robust floating point CMOS image sensor (CIS) is designed and tested. A detailed analysis
for signal-to-noise ratio (SNR) of the floating point CIS including the effect of the exponent …

Drain current variability in 45nm heavily pocket-implanted bulk MOSFET

CM Mezzomo, A Bajolet, A Cathignol… - 2010 Proceedings of …, 2010 - ieeexplore.ieee.org
Pocket architecture is a useful technique to eliminate short channel effects to provide smaller
transistors sizes. However, it has been shown that it has an important drawback on …

Drain-current variability in 45 nm bulk N-MOSFET with and without pocket-implants

CM Mezzomo, A Bajolet, A Cathignol, G Ghibaudo - Solid-state electronics, 2011 - Elsevier
In this work, the drain-current mismatch is characterized from linear to the saturation regime.
Characterizations are performed for N-MOS transistors with and without pocket-implants. A …