A survey on assertion-based hardware verification
Hardware verification of modern electronic systems has been identified as a major
bottleneck due to the increasing complexity and time-to-market constraints. One of the major …
bottleneck due to the increasing complexity and time-to-market constraints. One of the major …
Test generation using reinforcement learning for delay-based side-channel analysis
Reliability and trustworthiness are dominant factors in designing System-on-Chips (SoCs)
for a variety of applications. Malicious implants, such as hardware Trojans, can lead to …
for a variety of applications. Malicious implants, such as hardware Trojans, can lead to …
RevSCA-2.0: SCA-based formal verification of nontrivial multipliers using reverse engineering and local vanishing removal
The formal verification of integer multipliers is one of the important but challenging problems
in the verification community. Recently, the methods based on symbolic computer algebra …
in the verification community. Recently, the methods based on symbolic computer algebra …
Scalable hardware trojan activation by interleaving concrete simulation and symbolic execution
A Ahmed, F Farahmandi, Y Iskander… - … IEEE International Test …, 2018 - ieeexplore.ieee.org
Intellectual Property (IP) based System-on-Chip (SoC) design is a widely used practice
today. The IPs gathered from third-party vendors may not be trustworthy since they may …
today. The IPs gathered from third-party vendors may not be trustworthy since they may …
Understanding algebraic rewriting for arithmetic circuit verification: a bit-flow model
This paper addresses theoretical aspects of arithmetic circuit verification based on algebraic
rewriting. Its goal is to advance the understanding of algebraic techniques for arithmetic …
rewriting. Its goal is to advance the understanding of algebraic techniques for arithmetic …
Automated test generation for activation of assertions in RTL models
A major challenge in assertion-based validation is how to activate the assertions to ensure
that they are valid. While existing test generation using model checking is promising, it …
that they are valid. While existing test generation using model checking is promising, it …
Directed test generation for activation of security assertions in rtl models
Assertions are widely used for functional validation as well as coverage analysis for both
software and hardware designs. Assertions enable runtime error detection as well as faster …
software and hardware designs. Assertions enable runtime error detection as well as faster …
Scalable concolic testing of RTL models
Simulation is widely used for validation of Register-Transfer-Level (RTL) models. While
simulating with millions of random or constrained-random tests can cover majority of the …
simulating with millions of random or constrained-random tests can cover majority of the …
Automated trigger activation by repeated maximal clique sampling
Hardware Trojans are serious threat to security and reliability of computing systems. It is
hard to detect these malicious implants using traditional validation methods since an …
hard to detect these malicious implants using traditional validation methods since an …
Automated test generation for Trojan detection using delay-based side channel analysis
Side-channel analysis is widely used for hardware Trojan detection in integrated circuits by
analyzing various side-channel signatures, such as timing, power and path delay. Existing …
analyzing various side-channel signatures, such as timing, power and path delay. Existing …