[图书][B] Algorithms for VLSI physical design automation
NA Sherwani - 2012 - books.google.com
Algorithms for VLSI Physical Design Automation, Second Edition is a core reference text for
graduate students and CAD professionals. Based on the very successful First Edition, it …
graduate students and CAD professionals. Based on the very successful First Edition, it …
[图书][B] The VLSI handbook
WK Chen - 1999 - taylorfrancis.com
Over the years, the fundamentals of VLSI technology have evolved to include a wide range
of topics and a broad range of practices. To encompass such a vast amount of knowledge …
of topics and a broad range of practices. To encompass such a vast amount of knowledge …
Combinational logic synthesis for LUT based field programmable gate arrays
J Cong, Y Ding - ACM Transactions on Design Automation of Electronic …, 1996 - dl.acm.org
The increasing popularity of the field programmable gate-array (FPGA) technology has
generated a great deal of interest in the algorithmic study and tool development for FPGA …
generated a great deal of interest in the algorithmic study and tool development for FPGA …
Improved logic synthesis algorithms for table look up architectures
R Murgai, N Shenoy, RK Brayton… - … on Computer-Aided …, 1991 - computer.org
The authors address the problem of synthesis for a popular class of programmable gate
array architecture-the table look-up architectures. These use lookup table memories to …
array architecture-the table look-up architectures. These use lookup table memories to …
Technology mapping of lookup table-based FPGAs for performance
RJ Francis, J Rose, Z Vranesic - … on Computer-Aided Design Digest of …, 1991 - computer.org
A novel technology mapping algorithm that reduces the delay of combinational circuits
implemented with lookup-table-based field-programmable gate arrays (FPGAs) is …
implemented with lookup-table-based field-programmable gate arrays (FPGAs) is …
BDD-based logic synthesis for LUT-based FPGAs
Contemporary FPGA synthesis is a multiphase process that involves technology-
independent logic optimization followed by FPGA-specific mapping to a target FPGA …
independent logic optimization followed by FPGA-specific mapping to a target FPGA …
A tutorial on logic synthesis for lookup-table based FPGAs
Francis - 1992 IEEE/ACM International Conference on …, 1992 - ieeexplore.ieee.org
Discusses combinational logic synthesis for FPGAs that use lookup tables (LUTs). Issues
that differentiate LUT synthesis from conventional logic synthesis are emphasized. The …
that differentiate LUT synthesis from conventional logic synthesis are emphasized. The …
A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis
T Łuba, H Selvaraj - VLSI Design, 1995 - Wiley Online Library
An effective logic synthesis procedure based on parallel and serial decomposition of a
Boolean function is presented in this paper. The decomposition, carried out as the very first …
Boolean function is presented in this paper. The decomposition, carried out as the very first …
[PDF][PDF] A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to …
W Wan, MA Perkowski - Proceedings of the conference on European …, 1992 - cecs.pdx.edu
The paper presents a new approach to the decomposition of incompletely specified Boolean
functions and its application to LUT-based FPGA mapping. Three methods were developed …
functions and its application to LUT-based FPGA mapping. Three methods were developed …
Routability-driven technology mapping for lookup table-based FPGA's
M Schlag, J Kong, PK Chan - IEEE Transactions on Computer …, 1994 - ieeexplore.ieee.org
A new algorithm for technology mapping of lookup table-based Field-Programmable Gate
Arrays (FPGA's) is presented. It has the capability of producing compact designs (minimizing …
Arrays (FPGA's) is presented. It has the capability of producing compact designs (minimizing …