Binary convolutional neural network on RRAM
Recent progress in the machine learning field makes low bit-level Convolutional Neural
Networks (CNNs), even CNNs with binary weights and binary neurons, achieve satisfying …
Networks (CNNs), even CNNs with binary weights and binary neurons, achieve satisfying …
Low bit-width convolutional neural network on RRAM
The emerging resistive random-access memory (RRAM) has been widely applied in
accelerating the computing of deep neural networks. However, it is challenging to achieve …
accelerating the computing of deep neural networks. However, it is challenging to achieve …
Design of low power 4-bit flash ADC based on standard cells
MS Njinowa, HT Bui, FR Boyer - 2013 IEEE 11th International …, 2013 - ieeexplore.ieee.org
In this paper, a standard cell low power 4-bit flash analog-to-digital converter (ADC) is
proposed. The converter utilizes comparators created using only logic gates for converting …
proposed. The converter utilizes comparators created using only logic gates for converting …
Design of 4 bit flash ADC using TMCC & NOR ROM encoder in 90nm CMOS technology
KN Hosur, GV Attimarad, HM Kittur - … Conference on Trends in …, 2015 - ieeexplore.ieee.org
This paper presents design of 4 Bit Flash Analog to Digital Converter using a latest
comparator for voltage comparison called Threshold Modified Comparator Circuit (TMCC) …
comparator for voltage comparison called Threshold Modified Comparator Circuit (TMCC) …
Design of low power 5-bit hybrid flash ADC
SM Mayur, RK Siddharth, YBN Kumar… - 2016 IEEE Computer …, 2016 - ieeexplore.ieee.org
In this paper, a low power 5-bit hybrid flash architecture is proposed. The proposed analog-
to-digital converter (ADC) uses appropriate combination of both conventional double-tail …
to-digital converter (ADC) uses appropriate combination of both conventional double-tail …
Design of low power 4-bit 400MS/s standard cell based flash ADC
SM Mayur, RK Siddharth, NK YB… - 2017 IEEE Computer …, 2017 - ieeexplore.ieee.org
In this paper, a low power 4-bit 400 MS/s standard cell based flash Analog-to-Digital
Converter (ADC) is presented. The proposed flash ADC uses comparators based on the …
Converter (ADC) is presented. The proposed flash ADC uses comparators based on the …
Implementation of low supply rail-to-rail differential voltage comparator on flexible hardware for a flash ADC
A 4-bit flash ADC utilizing the advantage of digital-based differential voltage comparator is
presented in this paper. This circuit has an advantage of digital circuit concept and can be …
presented in this paper. This circuit has an advantage of digital circuit concept and can be …
Online handwritten formula recognition with integrated correction recognition and execution
A Kosmala, G Rigoll… - … Conference on Pattern …, 2000 - ieeexplore.ieee.org
Presents the extension of an approach for online handwritten formula recognition. The
introduction of some constraints concerning the handwriting production process and the …
introduction of some constraints concerning the handwriting production process and the …
Design of an efficient 8-bit flash ADC for optical communication receivers
The proposed 8-bit Flash ADC design does not require resistor ladder circuit and it can
operate at Giga Hz range with concurrent bubble error correction of 2nd order. It consists of …
operate at Giga Hz range with concurrent bubble error correction of 2nd order. It consists of …
Comparative study of comparator and encoder in a 4-bit Flash ADC using 0.18 μm CMOS technology
ISA Halim, SLM Hassan - 2012 International Symposium on …, 2012 - ieeexplore.ieee.org
This paper describes a comparative study of comparator and encoder in 4-bit Flash Analog
to Digital Converter (ADC) for Pipeline ADC to obtain a high speed ADC. In this paper, the …
to Digital Converter (ADC) for Pipeline ADC to obtain a high speed ADC. In this paper, the …