Process variation aware data management for STT-RAM cache design
The spin-transfer torque random access memory (STT-RAM) has gained increasing
attentions for its high density, fast read access, zero standby power, and good scalability …
attentions for its high density, fast read access, zero standby power, and good scalability …
Stt mram-based pufs
Physical Unclonable Functions are emerging cryptographic primitives used to implement
low-cost device authentication and secure secret key generation. In this paper we propose …
low-cost device authentication and secure secret key generation. In this paper we propose …
A dual-mode architecture for fast-switching STT-RAM
In the past, the spin-transfer torque RAM (STT-RAM) suffered from the slow write speed and
the high write energy consumption. The latest progress in device engineering has …
the high write energy consumption. The latest progress in device engineering has …
STT-MRAM-based strong PUF architecture
Physically Unclonable Functions (PUFs) are emerging cryptographic primitives used to
implement low-cost device authentication and secure secret key generation. Weak PUFs (ie …
implement low-cost device authentication and secure secret key generation. Weak PUFs (ie …
Power-aware voltage tuning for STT-MRAM reliability
EI Vatajelu, R Rodríguez-Montañés… - 2015 20th IEEE …, 2015 - ieeexplore.ieee.org
One of the most promising emerging memory technologies is the Spin-Transfer-Torque
Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low …
Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low …
Enhancing the L1 data cache design to mitigate HCI
Over the lifetime of a microprocessor, the Hot Carrier Injection (HCI) phenomenon degrades
the threshold voltage, which causes slower transistor switching and eventually results in …
the threshold voltage, which causes slower transistor switching and eventually results in …
[PDF][PDF] A survey of emerging architectural techniques for improving cache energy consumption
W Bhebhe, M Opoku Agyeman - … on Applied Electronics, 2016 - nectar.northampton.ac.uk
The search goes on for another ground breaking phenomenon to reduce the ever-
increasing disparity between the CPU performance and storage. There are encouraging …
increasing disparity between the CPU performance and storage. There are encouraging …
Global bit line restore by most significant bit of an address line
YH Chan, M Kugel, R Polig, TT Werner - US Patent 8,587,990, 2013 - Google Patents
An SRAM circuitry having SRAM cells for storing at least one data word of a length of at least
one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein …
one bit is provided. Each bit of the data words is stored in an assigned SRAM cell, wherein …
Reducing leakage power with BTB access prediction
R Kahn, S Weiss - Integration, 2010 - Elsevier
This paper investigates three architectural methods to reduce the leakage power dissipated
by the BTB data array. The first method (called here window) periodically places the entire …
by the BTB data array. The first method (called here window) periodically places the entire …
[图书][B] Predictable Task Migration Support and Static Task Partitioning for Scalable Multicore Real-Time Systems
A Sarkar - 2012 - search.proquest.com
Multicores are becoming ubiquitous, not only in general-purpose but also embedded
computing. This trend is a reflection of contemporary embedded applications posing steadily …
computing. This trend is a reflection of contemporary embedded applications posing steadily …