Software-based self-test of set-associative cache memories

S Di Carlo, P Prinetto, A Savino - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
Embedded microprocessor cache memories suffer from limited observability and
controllability creating problems during in-system tests. This paper presents a procedure to …

Software-based self-test for small caches in microprocessors

G Theodorou, N Kranitis, A Paschalis… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Nowadays, on-line testing is essential for modern microprocessors to detect latent defects
that either escape manufacturing testing or appear during system operation. Small …

Total power-optimal pipelining and parallel processing under process variations in nanometer technology

NS Kim, T Kgil, K Bowman, V De… - ICCAD-2005. IEEE/ACM …, 2005 - ieeexplore.ieee.org
This paper explores the effectiveness of the simultaneous application of pipelining and
parallel processing as a total power (static plus dynamic) reduction technique in digital …

A hybrid approach to the test of cache memory controllers embedded in SoCs

WJ Perez, J Velasco, D Ravotto… - 2008 14th IEEE …, 2008 - ieeexplore.ieee.org
Software-based self-test (SBST) is increasingly used for testing processor cores embedded
in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) …

Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation

JP Acle, R Cantoro, E Sánchez, MS Reorda… - Microprocessors and …, 2016 - Elsevier
The usage of electronic systems in safety-critical applications requires mechanisms for the
early detection of faults affecting the hardware while the system is in the field. When the …

A software-based self-test methodology for on-line testing of processor caches

G Theodorou, N Kranitis, A Paschalis… - 2011 IEEE …, 2011 - ieeexplore.ieee.org
Nowadays, on-line testing is essential for modern high-density microprocessors to detect
either latent hardware defects or new defects appearing during lifetime both in logic and …

[PDF][PDF] Analysis of multibackground memory testing techniques

I Mrozek - International Journal of Applied Mathematics and …, 2010 - intapi.sciendo.com
March tests are widely used in the process of RAM testing. This family of tests is very efficient
in the case of simple faults such as stuck-at or transition faults. In the case of a complex fault …

Using a CISC microcontroller to test embedded memories

A Van De Goor, S Hamdioui… - 13th IEEE Symposium …, 2010 - ieeexplore.ieee.org
Small microcontroller-based systems are omnipresent. Often, they do not have Memory BIST
(MBIST), or the MBIST is not available to the user. In such cases the CPU will be the only …

Software-based self-test strategy for data cache memories embedded in SoCs

JV Medina, D Ravotto, E Sanchez… - 2008 11th IEEE …, 2008 - ieeexplore.ieee.org
Testing SoC is a challenging task, especially when addressing complex and high-frequency
devices. Among the different techniques that can be exploited, Software-Based Selft-Test …

Marciatesta: an automatic generator of test programs for microprocessors' data caches

S Di Carlo, G Gambardella, M Indaco… - 2011 Asian Test …, 2011 - ieeexplore.ieee.org
SBST (Software Based Self-Testing) is an effective solution for in-system testing of SoCs
without any additional hardware requirement. SBST is particularly suited for embedded …