This paper presents an efficient method for online testing of NoC switches. This method
deals with control faults of NoC switches; ie the routing faults which cause NoC packets to …

This paper proposes an efficient test methodology to test switches in a network-on-chip
(NoC) architecture. A switch in a NoC consists of a number of ports and a router. Using the …

This paper presents efficient methods for online fault detection and diagnosis of Network-on-
Chip (NoC) switches. The fault model considered in this research is a system level fault …

Asynchronous design offers an attractive solution to address the problems faced by
networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication …

This paper addresses the important issue of fault tolerance in network-on-chip (NoC) and
presents an on-the-field test and configuration infrastructure for a 2-D-mesh NoC, which can …

This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip
network (NoC) for bisynchronous communication channels. Concurrent BIST operations are …

Asynchronous design offers an attractive solution to overcome the problems faced by
networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication …

The increasing multi-core system complexity with technology scaling introduces new
constraints and challenges to interconnection network design. Consequently, the research …

In this paper, two wrapper designs are proposed for core-based test application based on
Networks-on-Chip (NoC) reuse. It will be shown that the previously proposed NoC wrapper …

With the progress of deep submicron technology power consumption and temperature
related issues have become dominant factors for chip design. Therefore, very large-scale …