Thermal TSV optimization and hierarchical floorplanning for 3-D integrated circuits

Z Ren, A Alqahtani, N Bagherzadeh… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
While 3-D integrated circuits (ICs) offer many advantages over 2-D ICs, thermal
management challenges remain unresolved. Thermal through-silicon-vias (TTSVs) are …

A novel thermal-aware floorplanning and tsv assignment with game theory for fixed-outline 3-D ICs

W Guan, X Tang, H Lu, Y Zhang… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
High temperature or temperature nonuniformity has been considered as one of the most
challenging problems in three-dimensional integrated circuits (3-D ICs). There have been …

3D‐IC partitioning method based on genetic algorithm

NY Meitei, KL Baishnab… - IET Circuits, Devices & …, 2020 - Wiley Online Library
In this study, a new tier partitioning algorithm for three‐dimensional integrated circuits (3D
ICs) using a genetic algorithm (GA) is presented. Design parameters for the proposed 3D IC …

A machine learning-powered tier partitioning methodology for monolithic 3-D ICs

YC Lu, S Pentapati, L Zhu, G Murali… - … on Computer-Aided …, 2021 - ieeexplore.ieee.org
Tier partitioning is one of the most critical stages in monolithic 3-D (M3D) integrated circuits
(ICs) implementation flows. It transforms 2-D netlists into 3-D by performing tier assignment …

Floor planning of 3D IC design using hybrid multi-verse optimizer

S Pothiraj, JP Kadambarajan, P Kadarkarai - Wireless Personal …, 2021 - Springer
Several research works have been undergone in the 3D IC floor planning concepts due to
its higher demand and technological improvement. Floor planning is a complex step when …

Clustered fault tolerance TSV planning for 3-D integrated circuits

Q Xu, S Chen, X Xu, B Yu - IEEE Transactions on Computer …, 2017 - ieeexplore.ieee.org
In 3-D integrated circuits (3-D ICs), through silicon via (TSV) is a critical technique to provide
vertical connections. However, the yield and reliability challenge of TSV in industry is one of …

Design partitioning and layer assignment for 3D integrated circuits using tabu search and simulated annealing

SM Sait, FC Oughali, M Al-Asli - Journal of applied research and …, 2016 - scielo.org.mx
ABSTRACT 3D integrated circuits (3D-ICs) is an emerging technology with lots of potential.
3D-ICs enjoy small footprint area and vertical interconnections between different dies which …

Floorplanning for area optimization using parallel particle swarm optimization and sequence pair

A Prakash, RK Lal - Wireless Personal Communications, 2021 - Springer
In the integrated circuit (IC) designing floorplanning is an important phase in the process of
obtaining the layout of the circuit to be designed. The floorplanning determines the …

Physical design automation for 3D chip stacks: challenges and solutions

J Knechtel, J Lienig - Proceedings of the 2016 on International …, 2016 - dl.acm.org
The concept of 3D chip stacks has been advocated by both industry and academia for many
years, and hailed as one of the most promising approaches to meet ever-increasing …

TSV aware 3D IC partitioning with area optimization

JP Kadambarajan, S Pothiraj - Arabian Journal for Science and …, 2021 - Springer
A paradigm shift has been witnessed in microelectronic industry in recent days with more
and more research works focusing on transformation of Integrated Circuits from 2 to 3D …