A detailed roadmap from single gate to heterojunction TFET for next generation devices
JE Jeyanthi, TSA Samuel, AS Geege, P Vimala - Silicon, 2022 - Springer
Through the age of nanoelectronics, device dimensions are curbed, and the size of
transistors is rapidly reduced. Scaling down transistors results in high-speed switching …
transistors is rapidly reduced. Scaling down transistors results in high-speed switching …
Simulation-based analysis of ultra thin-body double gate ferroelectric TFET for an enhanced electric performance
The ultra thin body double gate FE layer TFET (UTB-DG-FE-TFET) is proposed and
investigated in this work. Electrical performance parameters such as surface potential ψ (x) …
investigated in this work. Electrical performance parameters such as surface potential ψ (x) …
Analytical modeling and simulation of gate-all-around Junctionless Mosfet for biosensing applications
A new analytical model for a Junctionless Field Effect Transistor that can be used in
biosensor applications is proposed in this research work. The Semiconductor device …
biosensor applications is proposed in this research work. The Semiconductor device …
Triple metal surrounding gate junctionless tunnel FET based 6T SRAM design for low leakage memory system
The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET
(TMSG–JL–TFET) based 6 T SRAM structure is demonstrated by employing Germanium …
(TMSG–JL–TFET) based 6 T SRAM structure is demonstrated by employing Germanium …
Investigation of ambipolar conduction and RF stability performance in novel germanium source dual halo dual dielectric triple material surrounding gate TFET
In this study, we present an ambipolar conduction and RF stability performance for a
Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel FET …
Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel FET …
Investigation of hetero gate oxide hetero stacked triple metal vertical tunnel FET with variable interface trap charges and temperature
S Bharali, B Choudhuri, B Bhowmick - Microelectronics Journal, 2024 - Elsevier
The performance of the hetero gate oxide hetero stacked triple metal vertical tunnel FET
(HGO-HS-TMG V-TFET) in both dc and analog/RF is examined in this work. GaSb (a low …
(HGO-HS-TMG V-TFET) in both dc and analog/RF is examined in this work. GaSb (a low …
Investigation and Analysis of Dual Metal Gate Overlap on Drain Side Tunneling Field Effect Transistor with Spacer in 10nm Node
S Howldar, B Balaji, K Srinivasa Rao - International Journal of Engineering, 2024 - ije.ir
This paper investigates the electrical behavior and performance of a Dual Metal Gate
Overlap on Drain Side Tunnel Field Effect Transistor with Spacer (DMG-ODS-TFET) in 10 …
Overlap on Drain Side Tunnel Field Effect Transistor with Spacer (DMG-ODS-TFET) in 10 …
Design and analysis of triple metal vertical TFET gate stacked with N-Type SiGe delta-doped layer
This work deals with the novel characterization of n+ SiGe δ-doped layer with the
combination of gate stacking method in Vertical TFET device by using TCAD simulation tool …
combination of gate stacking method in Vertical TFET device by using TCAD simulation tool …
A SVPWM control strategy for capacitor voltage balancing of flying capacitor based 4-level NPC inverter
R Palanisamy, V Shanmugasundaram… - Journal of Electrical …, 2020 - Springer
Abstract A Space Vector Pulse Width Modulation (SVPWM) control strategy is implemented
for capacitor voltage balancing of Flying Capacitor (FC) based 4-level Neutral Point …
for capacitor voltage balancing of Flying Capacitor (FC) based 4-level Neutral Point …
Performances of gate stacked heterojunction SELBOX and SOI tunnel FETs including interface trap charges: A simulation study
In this work, the influence of interface trap charges (ITCs) on electrical parameters of gate
stacked heterojunction silicon on insulator Tunnel FET (GSHJ-SOITFET) and GSHJ-TFET on …
stacked heterojunction silicon on insulator Tunnel FET (GSHJ-SOITFET) and GSHJ-TFET on …