Heterogeneous 2.5 D integration on through silicon interposer
Driven by the need to reduce the power consumption of mobile devices, and servers/data
centers, and yet continue to deliver improved performance and experience by the end …
centers, and yet continue to deliver improved performance and experience by the end …
Novel electrical and fluidic microbumps for silicon interposer and 3-D ICs
Fine-pitch electrical microbumps (25-μm diameter and 50-μm pitch) and annular-shaped
fluidic microbumps (150-μm inner diameter and 210-μm outer diameter) are presented to …
fluidic microbumps (150-μm inner diameter and 210-μm outer diameter) are presented to …
Full-chip power supply noise time-domain numerical modeling and analysis for single and stacked ICs
In this paper, a distributed circuit model for on-die power distribution network in single and 3-
D ICs is developed, and a set of difference equations are derived based on the circuit model …
D ICs is developed, and a set of difference equations are derived based on the circuit model …
Through-silicon-via-based decoupling capacitor stacked chip in 3-D-ICs
E Song, K Koo, JS Pak, J Kim - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
In this paper, a new decoupling capacitor stacked chip (DCSC) based on extra decoupling
capacitors and through-silicon-vias (TSVs) is proposed to overcome the narrow-bandwidth …
capacitors and through-silicon-vias (TSVs) is proposed to overcome the narrow-bandwidth …
Integrated thermal and power delivery network co-simulation framework for single-die and multi-die assemblies
Y Zhang, MS Bakir - IEEE Transactions on Components …, 2017 - ieeexplore.ieee.org
This paper presents a thermal and power delivery network (PDN) co-simulation framework
for single-die and emerging multi-die configurations that incorporates the interactions …
for single-die and emerging multi-die configurations that incorporates the interactions …
Alleviating through-silicon-via electromigration for 3-D integrated circuits taking advantage of self-healing effect
Three-dimensional integration is considered to be a promising technology to tackle the
global interconnect scaling problem for terascale integrated circuits (ICs). Three …
global interconnect scaling problem for terascale integrated circuits (ICs). Three …
Design, fabrication and assembly of a novel electrical and microfluidic I/Os for 3-D chip stack and silicon interposer
A novel chip I/O technology, which enables high-bandwidth signaling, embedded
microfluidic cooling and power delivery for high-performance 2.5 D (silicon interposer) and …
microfluidic cooling and power delivery for high-performance 2.5 D (silicon interposer) and …
A study of 3-D power delivery networks with multiple clock domains
A Todri-Sanial, Y Cheng - IEEE Transactions on Very Large …, 2016 - ieeexplore.ieee.org
Ongoing advancements in 3-D manufacturing are enabling 3-D ICs to contain several
processing cores, hardware accelerators, and dedicated peripherals. Most of these …
processing cores, hardware accelerators, and dedicated peripherals. Most of these …
High aspect ratio TSVs in micropin-fin heat sinks for 3D ICs
A Dembla, Y Zhang, MS Bakir - 2012 12th IEEE International …, 2012 - ieeexplore.ieee.org
Future high performance 3D systems require a systematic co-design of their electrical
interconnect network and their heat removal mechanism. This paper presents fine pitch (35 …
interconnect network and their heat removal mechanism. This paper presents fine pitch (35 …
New power delivery scheme for 3D ICs to minimize simultaneous switching noise for high speed I/Os
DC Zhang, M Swaminathan… - 2012 IEEE 21st …, 2012 - ieeexplore.ieee.org
New power delivery scheme for 3D ICs to minimize simultaneous switching noise for high
speed I/Os Page 1 New Power Delivery Scheme for 3D ICs to Minimize Simultaneous …
speed I/Os Page 1 New Power Delivery Scheme for 3D ICs to Minimize Simultaneous …