Although energy dissipation has improved with each new technology node, because SoCs
are integrating tens of million devices on-chip, the energy expended per operation has …

Low-voltage operation for memories is attractive because of lower leakage power and active
energy, but the challenges of SRAM design tend to increase at lower voltage. This paper …

Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and
leakage power, a dominating portion of the total power in modern ICs. Hence, energy …

A 256kb sub-threshold SRAM operates below 400mV from 0 to 85° C and is implemented in
65nm CMOS technology. For the same 6sigma static-noise margin, the sub-threshold SRAM …

This paper reviews the design challenges and techniques of high-performance SRAM in the
“End of Scaling” nanoscale CMOS technologies. The impacts of technology scaling, such as …

This paper describes a 32-Mb SRAM that has been designed and fabricated in a 65-nm low-
power CMOS Technology. The 62-mm 2 die features read-assist and write-assist circuit …

A 128 Mb 0.07 μm 2 6T high-density SRAM bitcell with write-assist circuitry has been
successfully implemented using 16 nm high-k metal gate FinFET technology. This study …

A 135-Mb 0.021-μm 2 6-T high-density SRAM bit cell with write-assist circuitries was
successfully implemented by using 5-nm HK-metal gate FinFET with EUV and high-mobility …

SRAM suffers read-disturb and write failures at a low supply voltage, especially at deep
subthreshold operation. This study proposes a 9T-SRAM cell with a data-aware-feedback …

Low voltage operation of digital circuits continues to be an attractive option for aggressive
power reduction. As standard SRAM bitcells are limited to operation in the strong-inversion …