Method for fabricating a semiconductor structure including a metal oxide interface with silicon
3,617,951 A 11/1971 Anderson 3,670,213 A 6/1972 Nakawaga et al. 3,766,370 A 10/1973
Walther 3,802,967 A 4/1974 Ladany et al. 3,914,137 A 10/1975 Huffman et al. 3,935,031 A …
Walther 3,802,967 A 4/1974 Ladany et al. 3,914,137 A 10/1975 Huffman et al. 3,935,031 A …
Method for producing virtual Ge substrates for III/V-integration on Si (001)
H Von Kaenel - US Patent 8,882,909, 2014 - Google Patents
US8882909B2 - Method for producing virtual Ge substrates for III/V-integration on Si(001) -
Google Patents US8882909B2 - Method for producing virtual Ge substrates for III/V-integration …
Google Patents US8882909B2 - Method for producing virtual Ge substrates for III/V-integration …
Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
AJ Lochtefeld, MT Currie, Z Cheng, J Fiorenza… - US Patent …, 2012 - Google Patents
(65) Prior Publication Data(Continued) US 2011 FOO49568 A1 Mar. 3, 2011 OTHER
PUBLICATIONS Related US Application Data 68 Applied Physics Letters 7, pp. 774-779 …
PUBLICATIONS Related US Application Data 68 Applied Physics Letters 7, pp. 774-779 …
Tri-gate field-effect transistors formed by aspect ratio trapping
AJ Lochtefeld - US Patent 7,799,592, 2010 - Google Patents
Semiconductor structures include a trench formed proximate a substrate including a first
semiconductor material. A crystalline material including a second semiconductor material …
semiconductor material. A crystalline material including a second semiconductor material …
Defect reduction using aspect ratio trapping
J Bai, JS Park, AJ Lochtefeld - US Patent 8,173,551, 2012 - Google Patents
US8173551B2 - Defect reduction using aspect ratio trapping - Google Patents
US8173551B2 - Defect reduction using aspect ratio trapping - Google Patents Defect …
US8173551B2 - Defect reduction using aspect ratio trapping - Google Patents Defect …
Semiconductor sensor structures with reduced dislocation defect densities
Z Cheng, JG Fiorenza, C Sheen… - US Patent 8,253,211, 2012 - Google Patents
5,091,333 5,091,767 5,093,699 5,098,850 5,105,247 5,108,947 5,156,995 5,159,413
5,164.359 5,166,767 5,223,043 5,236,546 5,238,869 5,256,594 5,269,852 5,269,876 …
5,164.359 5,166,767 5,223,043 5,236,546 5,238,869 5,256,594 5,269,852 5,269,876 …
Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
J Li, AJ Lochtefeld - US Patent 9,153,645, 2015 - Google Patents
US9153645B2 - Lattice-mismatched semiconductor structures with reduced dislocation
defect densities and related methods for device fabrication - Google Patents US9153645B2 …
defect densities and related methods for device fabrication - Google Patents US9153645B2 …
Lattice-mismatched semiconductor structures and related methods for device fabrication
AJ Lochtefeld - US Patent 7,777,250, 2010 - Google Patents
5,034,337 A 7, 1991 Mosher et al. 5,061,644 A 10, 1991 Yue et al. 5,091,333 A 2f1992 Fan
et al. 5,091,767 A 2f1992 Bean et al. 5,093,699 A 3, 1992 Weichold et al. 5,105,247 A …
et al. 5,091,767 A 2f1992 Bean et al. 5,093,699 A 3, 1992 Weichold et al. 5,105,247 A …
Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
AJ Lochtefeld, MT Currie, Z Cheng, J Fiorenza… - US Patent …, 2014 - Google Patents
Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited
area regions having upper por tions Substantially exhausted of threading dislocations, as …
area regions having upper por tions Substantially exhausted of threading dislocations, as …