Reliability-aware co-synthesis for embedded systems
As technology scales, transient faults have emerged as a key challenge for reliable
embedded system design. This paper proposes a design methodology that incorporates …
embedded system design. This paper proposes a design methodology that incorporates …
Integer linear programming-based optimization methodology for reliability and energy-aware high-level synthesis
Continuous decrease in the transistor technology sizes has enabled much denser
packaging of electronic components on chips, which has resulted in integrated circuits with …
packaging of electronic components on chips, which has resulted in integrated circuits with …
High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths
In this study, we propose a low-cost approach to error detection for arithmetic orientated data
paths by performing lightweight shadow computations in modulo-3 space for each main …
paths by performing lightweight shadow computations in modulo-3 space for each main …
Guaranteeing performance yield in high-level synthesis
WL Hung, X Wu, Y Xie - Proceedings of the 2006 IEEE/ACM international …, 2006 - dl.acm.org
Meeting timing constraint is one of the most important issues for modern design automation
tools. This situation is exacerbated with the existence of process variation. Current high-level …
tools. This situation is exacerbated with the existence of process variation. Current high-level …
On computing nano-architectures using unreliable nano-devices
This chapter will start with a brief review of nanoelectronic challenges while focusing on the
reliability challenge. One of the most recent call-to-arms [1] raises two fundamental …
reliability challenge. One of the most recent call-to-arms [1] raises two fundamental …
Reliability-aware operation chaining in high level synthesis
System reliability becomes one of the major design concerns in nanoscale VLSI
technologies. To cope with the increasing design complexity and the challenge of cost …
technologies. To cope with the increasing design complexity and the challenge of cost …
A high-level synthesis methodology for energy and reliability-oriented designs
Shrinking technology sizes of the CMOS circuits makes it possible to place more transistors
on a single chip at each technology generation. On the other hand, circuits become more …
on a single chip at each technology generation. On the other hand, circuits become more …
Serial addition: Locally connected architectures
V Beiu, S Aunet, J Nyathi, RR Rydberg… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
This paper will briefly review nanoelectronic challenges while focusing on reliability. We
shall present and analyze a series of CMOS-based examples for addition starting from the …
shall present and analyze a series of CMOS-based examples for addition starting from the …
A distributed clustered architecture to tackle delay variations in datapath synthesis
AA Del Barrio, J Cong… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
Due to the necessity of handling unexpected events in execution time, eg, to support
process variations, new mechanisms for dealing with every possible behavior of the …
process variations, new mechanisms for dealing with every possible behavior of the …
Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation
Y Hara-Azumi, H Tomiyama - International Symposium on …, 2013 - ieeexplore.ieee.org
Due to the continuous reduction in chip feature size and supply voltage, soft errors are
becoming a serious problem in the today's LSI design. Most literature on system-level …
becoming a serious problem in the today's LSI design. Most literature on system-level …