The automatic generation of RTL code (eg, Verilog) using natural language instructions and
large language models (LLMs) has attracted significant research interest recently. However …

This paper presents RTLFixer, a novel framework enabling automatic syntax errors fixing for
Verilog code with Large Language Models (LLMs). Despite LLM's promising capabilities …

As the ubiquity and complexity of system-on-chip (SoC) designs increase across electronic
devices, incorporating security into an SoC design flow poses significant challenges …

The increasing popularity of large language models (LLMs) has paved the way for their
application in diverse domains. This paper proposes a benchmarking framework tailored …

Assertion-based verification (ABV) is a critical method to ensure logic designs comply with
their architectural specifications. ABV requires assertions, which are generally converted …

Chip design is about to be revolutionized by the integration of large language, multimodal,
and circuit models (collectively LxMs). While exploring this exciting frontier with tremendous …

Recent advances in large language models have demonstrated their potential for automated
generation of hardware description language (HDL) code from high-level prompts …

The unprecedented success of Large Language Models (LLMs) like ChatGPT across
diverse domains such as natural language understanding and coding has paved the way for …

Large Language Models (LLMs) have recently shown promise in streamlining hardware
design processes by encapsulating vast amounts of domain-specific data. In addition, they …

Driven by Moore's Law, the complexity and scale of modern chip design are increasing
rapidly. Electronic Design Automation (EDA) has been widely applied to address the …