0003 2. Description 0004 The execution time of programs that have large code and/or data
footprints is significantly affected by the overhead of retrieving data from the memory system …

5,034,887 A 7/1991 Yasuiet a1. 5,301,295 A 4/1994 Learyetal. 5,455,913 A 10/1995
Shrocket a1. 5,546,548 A 8/1996 Chen et a1. 5,649,230 A 7/1997 LentZ 5,706,466 A 1/1998 …

(65) Prior Publication Data(57) ABSTRACT US 2006/0O856O2 A1 Apr. 20, 2006 An
arrangement is provided for an external agent to initiate (51) Int. Cl. data prefetches from a …

(57) ABSTRACT A circuit arrangement maintains power usage prediction information for one
or more functional units in branch pre diction logic for a processing unit such that the power …

(56) References Cited---A system and method for optimizing memory bus bandwidth, US
PATENT DOCUMENTS is achieved by utilization of the memory bus, either by utiliz …

Some embodiments provide a system that executes an appli cation. During operation, the
system obtains a resource list associated with the application and stores a set of resources …

A scheduler provided according to an aspect of the present invention provides higher priority
for data units in a low priority queue upon occurrence of a starvation condition, and to …

(57) ABSTRACT A memory controller for prefetching data for a processor, or CPU. ofa
computer system. The memory controller functions by interfacing the processor to System …

BACKGROUND 0002. In order to enhance the processing throughput of microprocessors,
processors typically utilize one or more levels of cache. These caches provide a faster …

An apparatus, system, and method are provided for managing errors in prefetched data. The
apparatus, system, and method identify prefetched data that contains an uncorrectable error …