TimingCamouflage+: Netlist security enhancement with unconventional timing
With recent advances in reverse engineering, attackers can reconstruct a netlist to
counterfeit chips by opening the die and scanning all layers of authentic chips. This …
counterfeit chips by opening the die and scanning all layers of authentic chips. This …
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units
GL Zhang, B Li, M Hashimoto… - Proceedings of the 55th …, 2018 - dl.acm.org
In digital circuit designs, sequential components such as flip-flops are used to synchronize
signal propagations. Logic computations are aligned at and thus isolated by flip-flop stages …
signal propagations. Logic computations are aligned at and thus isolated by flip-flop stages …
A high-performance parallel hardware architecture of SHA-256 hash in ASIC
R Wu, X Zhang, M Wang, L Wang - 2020 22nd International …, 2020 - ieeexplore.ieee.org
The SHA-256 algorithm is used to ensure the integrity and authenticity of data in order to
achieve a good security thus is playing an important role in various applications, such as e …
achieve a good security thus is playing an important role in various applications, such as e …
A learning-based timing prediction framework for wide supply voltage design
Wide voltage design provides the tremendous benefits for state-of-the-art circuit design in
terms of power consumption reduction and energy efficiency enhancement. The traditional …
terms of power consumption reduction and energy efficiency enhancement. The traditional …
Timing analysis and optimization method with interdependent flip-flop timing model for near-threshold design
P Cao, Y Qin, H Jiang - Electronics, 2022 - mdpi.com
Near-threshold Voltage (NTV) design is receiving wide attention due to remarkable energy
efficiency improvement at the cost of performance degradation. The interdependency …
efficiency improvement at the cost of performance degradation. The interdependency …
Topology-aided multicorner timing predictor for wide voltage design
In wide voltage design, timing needs to be verified at a very large number of corners. This
article presents a learning-based approach to predict path timing for multiple unknown …
article presents a learning-based approach to predict path timing for multiple unknown …
VirtualSync+: Timing Optimization With Virtual Synchronization
In digital circuit designs, sequential components such as flip-flops are used to synchronize
signal propagations. Logic computations are aligned at and thus isolated by flip-flop stages …
signal propagations. Logic computations are aligned at and thus isolated by flip-flop stages …
A modified method for general LDPC bit-flipping decoding
R Wu, L Wang, H Feng, W He - … of the 7th International Conference on …, 2019 - dl.acm.org
A modified method for general LDPC bit-flipping decoding is proposed in this paper. The
proposed method consists of two parts: multi-bit flipping judgement algorithm and multi-bit …
proposed method consists of two parts: multi-bit flipping judgement algorithm and multi-bit …
A full-transistor fine-grain multilevel delay element with compact regularity layout
B Liu, Z Huang, J Zhang, M Liu, Q Meng - Analog Integrated Circuits and …, 2020 - Springer
This paper proposes a full-transistor multilevel delay element (DE) implemented by 65
nm/1.8 V CMOS technology. 10 mV/LSB and 50 mV/LSB control voltages are employed to …
nm/1.8 V CMOS technology. 10 mV/LSB and 50 mV/LSB control voltages are employed to …
Advanced Timing for High-Performance Design and Security of Digital Circuits
L Zhang - 2018 - mediatum.ub.tum.de
To deal with process variations at advanced technology nodes, post-silicon clock tuning is
explored to adjust the timing properties of chips after manufacturing to improve circuit …
explored to adjust the timing properties of chips after manufacturing to improve circuit …