An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-
semiconductor-vias. The trap rich layer is formed above the circuit layer. The through …

We utilize electrically detected magnetic resonance (EDMR) measurements to compare high-
field stressed, and gamma irradiated Si/SiO 2 metal–oxide–silicon (MOS) structures. We …

This study proposes a new method to measure the polarization charge of ferroelectric field-
effect transistors (FeFETs) using a pulse generator and source measurement unit (SMU) and …

It is well known that the interface traps at the Si/SiO2 interface in MOS (metal-oxide-
semiconductor) structures play an important role in determining the threshold voltage (VT) …

257/774 2010/0243040 A1 9/2010 Kim 2012/0074579 Al 3/2012 Su et al. 2012/0146193 Al
6/2012 Stuber et al. 2012/0161310 Al 6/2012 Brindle et al. 2013/0037922 A1 2/2013 …

Temperature dependence under various HCD conditions was analyzed in 14 nm node
FinFETs. Unlike oxide traps, interface traps show different temperature dependence …

An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer
is formed with an active device layer and a metal interconnect layer. The trap rich layer is …

A differential body-factor technique (DBT) is proposed for characterization of interface traps
in MOSFETs employing the differential body factor dm/dV GS instead of the subthreshold …

Optical subthreshold current method (OSCM) is proposed for characterizing the interface
states in MOS systems using the current-voltage characteristics under a photonic excitation …

A new sub-bandgap photonic gated-diode method is proposed to extract the energy-
dependent and spatial distributions of traps at the SiO2/Si interface in MOSFETs. For the …