This paper proposes a low-complexity min-sum algorithm for decoding low-density parity-
check codes. It is an improved version of the single-minimum algorithm where the two …

In this work, we consider high-rate error-control systems for storage devices using multi-level
per cell (MLC) NAND flash memories. Aiming at achieving a strong error-correcting …

This paper presents a normalized probabilistic min-sum algorithm for low-density parity-
check (LDPC) codes, where a probabilistic second minimum value, instead of the true …

This paper presents an efficient multi-standard low-density parity-check (LDPC) decoder
architecture using a shuffled decoding algorithm, where variable nodes are divided into …

When residual belief-propagation (RBP), which is a kind of informed dynamic scheduling
(IDS), is applied to low-density parity-check (LDPC) codes, the convergence speed in error …

Although Latin square is a well-known algorithm to construct low-density parity-check
(LDPC) codes for satisfying long code length, high code-rate, good correcting capability, and …

For high-rate low-density parity-check (LDPC) codes, layered decoding processing can be
reordered such that the first-in-first-out (FIFO) buffer that stores variable-to-check (V2C) …

This paper presents a high-throughput decoder architecture for non-binary low-density parity-
check (LDPC) codes, where the q-ary sum-product algorithm (QSPA) in the log domain is …

This paper presents a high-throughput, area-efficient and energy-efficient iterative detection
and decoding (IDD) receiver for low-density parity-check (LDPC)-coded multiple-input …

Configurable permutators in an LDPC decoder are provided. A partially-parallel architecture
combined with the proposed permutators is used to mitigate the increase in implementa tion …