CKV (fy) operative to select one of the plurality of phases. A phase detection circuit is
coupled to the switch and is operable to receive a selected phase and to provide digital …

An embodiment of the present invention provides a phase locked loop that operates on
clock signals derived from an RF clock signal generated by the phase locked loop. A …

Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device
based on a feedback signal from the device. The feedback signal can provide phase …

An embodiment of the present invention provides a phase locked loop that operates on
clock signals derived from an RF clock signal generated by the phase locked loop. A …

2008-02-05 Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS
INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE …

(57) ABSTRACT A timestamp-based all digital phase locked loop is utilized for clock
synchronization for Circuit Emulation Service (“CES) over packet networks. The all digital …

A variable bandwidth phase locked loop (PLL) includes renormalizable circuitry configured
to allow a gain of the PLL to be changed without causing a disturbance, and a phase …

Abstract A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC)
that receives a Digitally Controlled Oscillator (DCO) output signal and a reference clock and …

An all-digital phase locked loop (ADPLL) generates a feed back word representing a
continuous-time oscillating signal. The ADPLL includes a time-to-digital converter (TDC) con …

(57) ABSTRACT A novel and useful apparatus for and method of software based phase
locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit …