This paper reviews recent important results in the development of neuromorphic network
architectures ('CrossNets') for future hybrid semiconductor/nanodevice‐integrated circuits. In …

This paper describes a digital logic architecture for 'CMOL'hybrid circuits which combine a
semiconductor–transistor (CMOS) stack and two levels of parallel nanowires, with molecular …

While most of the electronics industry is dependent on the ever-decreasing size of
lithographic transistors, this scaling cannot continue indefinitely. Nanoelectronics (circuits …

Benefiting from Spin Transfer Torque (STT) switching approach, second generation of
Magnetic RAM (MRAM) promises low power, great miniaturization prospective (< 22nm) and …

This article provides an overview of several logic redundancy schemes, including von
Neumann's multiplexing logic, N-tuple modular redundancy, and interwoven redundant …

Motivated by the need for economical fault-tolerant designs for nanoarchitectures, we
explore a novel multiplexing-based redundant design scheme at small (/spl les/100) and …

In nano-domain logic circuits, errors generated are transient in nature and will arise due to
the uncertainty or the unreliability of the computing element itself. This type of errors-which …

Both von Neumann's NAND multiplexing, based on a massive duplication of imperfect
devices and randomized imperfect interconnects, and reconfigurable architectures have …

In this paper, we present a hardware technique, called self-repairing array structures
(SRAS), for masking hard faults in microprocessor array structures, such as the reorder …

Nanoelectronic devices are anticipated to become exceedingly noisy as they are scaled
towards thermodynamic limits. Hence the development of nanoscale classical information …