AI/ML algorithms and applications in VLSI design and technology
An evident challenge ahead for the integrated circuit (IC) industry is the investigation and
development of methods to reduce the design complexity ensuing from growing process …
development of methods to reduce the design complexity ensuing from growing process …
DE-HNN: An effective neural model for Circuit Netlist representation
The run-time for optimization tools used in chip design has grown with the complexity of
designs to the point where it can take several days to go through one design cycle which …
designs to the point where it can take several days to go through one design cycle which …
Towards machine learning-based fpga backend flow: Challenges and opportunities
I Taj, U Farooq - Electronics, 2023 - mdpi.com
Field-Programmable Gate Array (FPGA) is at the core of System on Chip (SoC) design
across various Industry 5.0 digital systems—healthcare devices, farming equipment …
across various Industry 5.0 digital systems—healthcare devices, farming equipment …
RLPlace: Using reinforcement learning and smart perturbations to optimize FPGA placement
Simulated annealing (SA) is one of the most common FPGA placement techniques, and is
used both as a standalone algorithm and to improve an initial analytical placement. While …
used both as a standalone algorithm and to improve an initial analytical placement. While …
LHNN: Lattice hypergraph neural network for VLSI congestion prediction
Precise congestion prediction from a placement solution plays a crucial role in circuit
placement. This work proposes the lattice hypergraph (LH-graph), a novel graph formulation …
placement. This work proposes the lattice hypergraph (LH-graph), a novel graph formulation …
Towards machine learning for placement and routing in chip design: a methodological overview
Placement and routing are two indispensable and challenging (NP-hard) tasks in modern
chip design flows. Compared with traditional solvers using heuristics or expert-well …
chip design flows. Compared with traditional solvers using heuristics or expert-well …
Efficient FPGA routing using reinforcement learning
With every new generation, Field Programmable Gate Arrays (FPGAs) are getting more
complex and so are their back end flow. Routing is an important step of FPGA back end flow …
complex and so are their back end flow. Routing is an important step of FPGA back end flow …
Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning
Over the past few years, the computation capability of field-programmable gate arrays
(FPGAs) has increased tremendously. This has led to the increase in the complexity of the …
(FPGAs) has increased tremendously. This has led to the increase in the complexity of the …
A deep-learning framework for predicting congestion during FPGA placement
D Maarouff, A Shamli, T Martin… - … Conference on Field …, 2020 - ieeexplore.ieee.org
The ability to quickly and accurately predict congestion has emerged as one of the most
critical problems during placement. In this paper, we present DLCong, a deep learning …
critical problems during placement. In this paper, we present DLCong, a deep learning …
Predicting routability of FPGA design by learning complex network images
T Nie, Y Wang, P Liu, K Zhao, Z Wang - Expert Systems with Applications, 2025 - Elsevier
Accurately and efficiently predicting the routability of modern FPGAs in the early stages is
significant for achieving ultimate optimization. We propose a novel approach for FPGA …
significant for achieving ultimate optimization. We propose a novel approach for FPGA …