[图书][B] VLSI test principles and architectures: design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …
design a testable and quality product, drive down test cost, improve product quality and …
Survey of test vector compression techniques
NA Touba - IEEE Design & test of computers, 2006 - ieeexplore.ieee.org
Test data compression consists of test vector compression on the input side and response,
compaction on the output side. This vector compression has been an active area of …
compaction on the output side. This vector compression has been an active area of …
[图书][B] Electronic design automation: synthesis, verification, and test
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
[图书][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
XPAND: An efficient test stimulus compression technique
Combinational circuits implemented with exclusive-or gates are used for on-chip generation
of deterministic test patterns from compressed seeds. Unlike major test compression …
of deterministic test patterns from compressed seeds. Unlike major test compression …
Test data compression for system-on-a-chip using extended frequency-directed run-length code
AH El-Maleh - IET Computers & Digital Techniques, 2008 - IET
One of the major challenges in testing a system-on-a-chip is dealing with the large volume of
test data. To reduce the volume of test data, several test data compression techniques have …
test data. To reduce the volume of test data, several test data compression techniques have …
Historical perspective on scan compression
R Kapur, S Mitra, TW Williams - IEEE Design & Test of …, 2008 - ieeexplore.ieee.org
Since gaining popularity in the late 1990s, the term" scan compression" has maintained a
solid hold within the IC test lexicon. In recent years, however, this technology has taken the …
solid hold within the IC test lexicon. In recent years, however, this technology has taken the …
Trimodal scan-based test paradigm
This paper presents a novel scan-based design for test (DFT) paradigm. Compared with
conventional scan, the presented approach either significantly reduces test application time …
conventional scan, the presented approach either significantly reduces test application time …
Method and apparatus for testing 3D integrated circuits
BACKGROUND Three-dimensional (3D) packaging is short for 3D die stacking using
through-silicon Vias (TSVs), conceptually similar to nails, as opposed to wire-bonds for …
through-silicon Vias (TSVs), conceptually similar to nails, as opposed to wire-bonds for …
Using limited dependence sequential expansion for decompressing test vectors
Existing techniques that incorporate decompressor constraints in the ATPG
search/backtrace (eg, Illinois scan) are based on combinational expansion in which each …
search/backtrace (eg, Illinois scan) are based on combinational expansion in which each …