High speed most significant bit first truncated multiplier
C Chinta, RB Deshmukh - 2018 9th International Conference …, 2018 - ieeexplore.ieee.org
This paper proposes a high-speed MSB first multiplier which works efficiently when
successive inputs show gradual change which is usually the case for analog signals …
successive inputs show gradual change which is usually the case for analog signals …
[引用][C] Distributed Memory based Architecture for Multiplier
SA Mastani, S Kannappan - International Journal of …, 2022 - University of Bahrain