ECG arrhythmia classification on an ultra-low-power microcontroller

R Dekimpe, D Bol - IEEE Transactions on Biomedical Circuits …, 2022 - ieeexplore.ieee.org
Wearable biomedical systems allow doctors to continuously monitor their patients over
longer periods, which is especially useful to detect rarely occurring events such as cardiac …

Comprehensive analytical comparison of ring oscillators in FDSOI technology: Current starving versus back-bias control

M Schramme, L Van Brandt… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator
(FDSOI) CMOS technologies, which can be used to control the oscillation frequency of …

UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI

M Schramme, D Bol - … Transactions on Circuits and Systems I …, 2023 - ieeexplore.ieee.org
Sensitivity to process, voltage, and temperature (PVT) variations constitutes a serious
obstacle in ultralow-voltage/ultralow-power (ULV/ULP) circuits and systems. To address this …

A sub-mw cortex-m4 microcontroller design for iot software-defined radios

M Xhonneux, J Louveaux, D Bol - IEEE Open Journal of …, 2023 - ieeexplore.ieee.org
We present an Internet-of-Things (IoT) software-defined radio platform based on an ultra low-
power microcontroller. Whereas conventional wireless IoT radios often implement a single …

Implementing a LoRa software-defined radio on a general-purpose ULP microcontroller

M Xhonneux, J Louveaux, D Bol - 2021 IEEE Workshop on …, 2021 - ieeexplore.ieee.org
Emerging Internet-of-Things sensing applications rely on ultra low-power (ULP)
microcontroller units (MCUs) that wirelessly transmit data to the cloud. Typical MCUs …

A 7T-NDR dual-supply 28-nm FD-SOI ultra-low power SRAM with 0.23-nW/kB sleep retention and 0.8 pJ/32b access at 64 MHz with forward back bias

A Kneip, D Bol - IEEE Transactions on Circuits and Systems I …, 2023 - ieeexplore.ieee.org
This work presents a 16kB ultra-low power (ULP) SRAM macro in 28nm FD-SOI with high
energy efficiency in active mode and ultra-low leakage (ULL) in sleep mode, embedded in …

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI

H Bauer, M Stolba, S Scholze, D Walter… - 2023 20th …, 2023 - ieeexplore.ieee.org
We present a low-power, energy efficient 32-bit RISCV microprocessor unit (MCU) in 22 nm
FD-SOI. It achieves ultra-low leakage, even at high temperatures, by using an adaptive …

Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μW

M Gonzalez, D Bol - 2023 Design, Automation & Test in Europe …, 2023 - ieeexplore.ieee.org
Hierarchical optimization methods used in the design of complex mixed-signal systems
require accurate behavioral models to avoid the long simulation times of transistor-level …

Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores

J Kadomoto, H Irie, S Sakai - 2022 IEEE 15th International …, 2022 - ieeexplore.ieee.org
The increase in Internet of Things (IoT) applications has triggered the development of
energy-efficient embedded SoCs that can utilize limited energy sources. Relatively simple …

[PDF][PDF] Software-defined and multi-user LPWAN radios: towards preventing the obsolescence of IoT devices

M Xhonneux - 2022 - dial.uclouvain.be
With the exponential deployment of Internet-of-Things (IoT) connected devices, massive
networks relying on first-generation low-power wide-area network (LPWAN) protocols begin …