Past research has proposed numerous hardware prefetching techniques, most of which rely
on exploiting one specific type of program context information (eg, program counter …

3D perception in point clouds is transforming the perception ability of future intelligent
machines. Point cloud algorithms, however, are plagued by irregular memory accesses …

We present Decoupled Vector Runahead (DVR), an in-core prefetching technique,
executing separately to the main application thread, that exploits massive amounts of …

Long-latency load requests continue to limit the performance of modern high-performance
processors. To increase the latency tolerance of a processor, architects have primarily relied …

This paper presents Tartan, a CPU architecture designed for a wide range of robotic
applications. Tartan provides architectural support for common robotic kernels, ensuring its …

Load instructions often limit instruction-level parallelism (ILP) in modern processors due to
data and resource dependences they cause. Prior techniques like Load Value Prediction …

Indirect memory accesses (IMAs, ie, A [f (B [i])]) are typical memory access patterns in
applications such as graph analysis, machine learning, and database. IMAs are composed …

Indirect memory access is a critical bottleneck for modern CPUs, especially for graph
analysis and sparse linear algebra applications, where the values of one data array are …

Decreasing voltage levels and continued transistor scaling have drastically increased the
chance of a processor bit encountering a soft error. We find that the microarchitecture state …

Superscalar out-of-order cores deliver high performance at the cost of increased complexity
and power budget. In-order cores, in contrast, are less complex and have a smaller power …