IoTs enable active contour modeling based energy efficient and thermal aware object tracking on FPGA
Object tracking based on active contour modeling is an image processing related
technology that uses snapshots of the object under consideration to track it via robot in the …
technology that uses snapshots of the object under consideration to track it via robot in the …
Performance evaluation of FIR filter after implementation on different FPGA and SOC and its utilization in communication and network
There are many areas of communication and network, which have open scope to use FIR
filter. Therefore, energy efficient FIR filter will increase lifetime of network and FIR filter with …
filter. Therefore, energy efficient FIR filter will increase lifetime of network and FIR filter with …
Different I/O standard and technology based thermal aware energy efficient Vedic multiplier design for green wireless communication on FPGA
This paper deals with low power multiplier design that plays a significant role in green
wireless communications systems. Over the period of time, researchers have proposed …
wireless communications systems. Over the period of time, researchers have proposed …
Internet of things enabled energy efficient green communication on FPGA
In this paper, we observed the vast effect of internet on our lives. Internet has acquired a
space in our everyday work and we are in a way dependent on it. This paper inspired by …
space in our everyday work and we are in a way dependent on it. This paper inspired by …
Design of a Power Efficient Model of PWM Generator for Green Communication using High Performance FPGAs
Aims: This paper will focus on promoting the ideas of green communication. Background:
Pulse Width Modulation (PWM) generator is used to control the power transfer in any …
Pulse Width Modulation (PWM) generator is used to control the power transfer in any …
Evaluating clustering algorithms: Cluster quality and feature selection in content-based image clustering
M Sileshi, B Gamback - 2009 WRI World Congress on …, 2009 - ieeexplore.ieee.org
The paper presents an evaluation of four clustering algorithms: k-means, average linkage,
complete linkage, and Wardpsilas method, with the latter three being different hierarchical …
complete linkage, and Wardpsilas method, with the latter three being different hierarchical …
Capacitance scaling with different IO standard based energy efficient bio-medical wrist watch design on 28nm FGPA
In this paper, we have designed an energy efficient wrist watch on 28nm FPGA. The code
has been implemented in Xilinx ISE Design Suite 14.2. The device used is XC7K160T …
has been implemented in Xilinx ISE Design Suite 14.2. The device used is XC7K160T …
Low Voltage Digitally Controlled Impedance Based Energy Efficient Vedic Multiplier Design on 28nm FPGA
Low Voltage Digitally Controlled Impedance (LVDCI) is an I/O standard available on FPGA.
This design is LVDCI IO standard based Energy Efficient Vedic Multiplier Design on FPGA …
This design is LVDCI IO standard based Energy Efficient Vedic Multiplier Design on FPGA …
Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA
R Saini, N Bansal, M Bansal, L Kalra… - Advanced Materials …, 2015 - Trans Tech Publ
—Thermal aware design is currently gaining importance in VLSI research domain. In this
work, we are going to design thermal aware energy efficient ROM on Virtex-5 FPGA …
work, we are going to design thermal aware energy efficient ROM on Virtex-5 FPGA …
[PDF][PDF] Design of Low Power Digital Clock on FPGA using Different IO Standards
B Singh, A Chodha, B Sharma… - Indian Journal …, 2016 - sciresol.s3.us-east-2.amazonaws …
Objective: This paper analyzes the power of a digital clock with the help of Xilinx ISE V-14.2
and executing it on virtex-6 FPGA and Spartan 3E FPGA. Methods: On FPGA we use Verilog …
and executing it on virtex-6 FPGA and Spartan 3E FPGA. Methods: On FPGA we use Verilog …