Pf-dram: a precharge-free dram structure

N Rohbani, S Darabi… - 2021 ACM/IEEE 48th …, 2021 - ieeexplore.ieee.org
Although DRAM capacity and bandwidth have increased sharply by the advances in
technology and standards, its latency and energy per access have remained almost …

A low-overhead integrated aging and SEU sensor

N Rohbani, SG Miremadi - IEEE Transactions on Device and …, 2018 - ieeexplore.ieee.org
Aging has become a critical CMOS reliability issue in nanoscales. In general, the aging
effect is exhibited as an increase in the delay of the combinational parts and robustness …

Compact modeling of dynamic trap density evolution for predicting circuit-performance aging

M Miura-Mattausch, H Miyamoto, H Kikuchihara… - Microelectronics …, 2018 - Elsevier
It is shown that a compact MOSFET-aging model for circuit simulation is possible by
considering the dynamic trap-density increase, which is induced during circuit operation …

An aging simulation method based on the change of input vector inside the critical path

Q Sang, X Yang, L Wang, S Wang… - Journal of Physics …, 2024 - iopscience.iop.org
With the large-scale expansion and process shrinking of modern integrated circuits, aging
has become one of the main factors threatening circuit reliability. To evaluate the impact of …

Power reduction and bti mitigation of data-cache memory based on the storage management of narrow-width values

N Rohbani, H Gau, S Mohammadinejad… - … Transactions on Very …, 2019 - ieeexplore.ieee.org
Power dissipation of on-chip cache memories contributes a large portion of a processor's
power consumption. Therefore, power management of cache memories is crucial in modern …

Nvdl-cache: Narrow-width value aware variable delay low-power data cache

N Rohbani, TK Maiti, D Navarro… - 2019 IEEE 37th …, 2019 - ieeexplore.ieee.org
Cache memories dissipate a large portion of processors' power budget. On the other hand,
due to unbalanced stress condition on their SRAMs, aging of cache memories is one of the …