Defect reduction for formation of epitaxial layer in source and drain regions
CH Tsai, CC Su, TM Kwok - US Patent 9,076,734, 2015 - Google Patents
The embodiments of mechanisms for forming source/drain (S/D) regions of field effect
transistors (FETs) described enable forming an epitaxially grown silicon-containing layer …
transistors (FETs) described enable forming an epitaxially grown silicon-containing layer …
Device structure and method for reducing silicide encroachment
RS Chau, E Andideh, MC Taylor, CH Jan… - US Patent …, 2004 - Google Patents
In a first embodiment of the present invention, a Semi conductor device having a novel
Spacer Structure and its method of fabrication is described. According to the first …
Spacer Structure and its method of fabrication is described. According to the first …
Method of forming a transistor
RS Chau, CH Jan, P Packan, MC Taylor - US Patent 5,908,313, 1999 - Google Patents
US5908313A - Method of forming a transistor - Google Patents US5908313A - Method of
forming a transistor - Google Patents Method of forming a transistor Download PDF Info …
forming a transistor - Google Patents Method of forming a transistor Download PDF Info …
Transistor with low resistance tip and method of fabrication in a CMOS process
RS Chau, CH Jan, CH Chern, LD Yau - US Patent 6,165,826, 2000 - Google Patents
A novel transistor with a low resistance ultra shallow tip region and its method of fabrication
in a complementary metal oxide semiconductor (CMOS) process. According to the preferred …
in a complementary metal oxide semiconductor (CMOS) process. According to the preferred …
RF circuits including transistors having strained material layers
G Braithwaite, R Hammond, M Currie - US Patent 7,709,828, 2010 - Google Patents
(52) US Cl................... 257/24; 257/219; 257/E29. 012 (58) Field of Classification
Search.................... 257/24 See application file for complete search history. Circuits for …
Search.................... 257/24 See application file for complete search history. Circuits for …
Shallow trench isolation process
MT Currie, AJ Lochtefeld - US Patent 7,504,704, 2009 - Google Patents
US7504704B2 - Shallow trench isolation process - Google Patents US7504704B2 -
Shallow trench isolation process - Google Patents Shallow trench isolation process …
Shallow trench isolation process - Google Patents Shallow trench isolation process …
Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
EA Fitzgerald - US Patent 7,256,142, 2007 - Google Patents
4,997,776 5,013,681 5,034,348 5,089,872 5,091,767 5,108,946 5,155,571 5,166,084
5,177.583 5, 198,689 5,202,284 5,207,864 5,208, 182 5,212,110 5,212,112 5,217.923 …
5,177.583 5, 198,689 5,202,284 5,207,864 5,208, 182 5,212,110 5,212,112 5,217.923 …
Method and apparatus for controlling the thickness of a selective epitaxial growth layer
PR Besser, EN Paton, GE William - US Patent 7,402,207, 2008 - Google Patents
Methods and systems for permitting thickness control of the selective epitaxial growth (SEG)
layer in a semiconductor manufacturing process, for example raised source/drain …
layer in a semiconductor manufacturing process, for example raised source/drain …
Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
TA Langdo, AJ Lochtefeld - US Patent 7,122,449, 2006 - Google Patents
Methods for fabricating facetless semiconductor structures using commercially available
chemical vapor deposition systems are disclosed herein. A key aspect of the invention …
chemical vapor deposition systems are disclosed herein. A key aspect of the invention …
Strained-semiconductor-on-insulator device structures with elevated source/drain regions
TA Langdo, MT Currie, R Hammond… - US Patent …, 2008 - Google Patents
US7420201B2 - Strained-semiconductor-on-insulator device structures with elevated source/drain
regions - Google Patents US7420201B2 - Strained-semiconductor-on-insulator device …
regions - Google Patents US7420201B2 - Strained-semiconductor-on-insulator device …