Automatic detection of change in PLL locking trend
TH Tsai, CH Chang - US Patent 9,853,807, 2017 - Google Patents
A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an
example, of the present disclosure operates in a frequency tracking mode to adjust a …
example, of the present disclosure operates in a frequency tracking mode to adjust a …
Hybrid phase lock loop
TH Tsai, RB Sheen, CH Chang, CH Hsieh - US Patent 10,164,649, 2018 - Google Patents
Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital
controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital …
controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital …
PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications
FW Kuo, CP Jou, LC Cho, C Huan-Neng… - US Patent …, 2019 - Google Patents
US10171089B2 - PVT-free calibration function using a doubler circuit for TDC resolution in
ADPLL applications - Google Patents US10171089B2 - PVT-free calibration function using …
ADPLL applications - Google Patents US10171089B2 - PVT-free calibration function using …
Regulated voltage systems and methods using intrinsically varied process characteristics
CL Tai - US Patent 10,637,351, 2020 - Google Patents
A regulator system includes a multi-bit detector system and a multi-cell charge/discharge
circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of …
circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of …
Automatic detection of change in PLL locking trend
TH Tsai, CH Chang - US Patent 10,644,869, 2020 - Google Patents
A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an
example, of the present disclosure operates in a frequency tracking mode to adjust a …
example, of the present disclosure operates in a frequency tracking mode to adjust a …
Automatic detection of change in PLL locking trend
TH Tsai, CH Chang - US Patent 10,090,994, 2018 - Google Patents
A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an
example, of the present disclosure operates in a frequency tracking mode to adjust a …
example, of the present disclosure operates in a frequency tracking mode to adjust a …
Hybrid phase lock loop
TH Tsai, CH Chang, RB Sheen, CH Hsieh - US Patent 10,523,221, 2019 - Google Patents
Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital
controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital …
controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital …
Automatic detection of change in PLL locking trend
TH Tsai, CH Chang - US Patent 10,439,794, 2019 - Google Patents
A phase lock loop (PLL), such as an all digital phase lock loop (ADPLL) to provide an
example, of the present disclosure operates in a frequency tracking mode to adjust a …
example, of the present disclosure operates in a frequency tracking mode to adjust a …
Regulated voltage systems and methods using intrinsically varied process characteristics
CL Tai - US Patent 11,239,749, 2022 - Google Patents
A regulator system includes a multi-bit detector system and a multi-cell charge/discharge
circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of …
circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of …
DLL calibration method for fast frequency change without re-locking
M Nummer, R Abbott - US Patent 9,716,507, 2017 - Google Patents
BACKGROUND DDR stands for double data rate. Physical DDR interfaces (PHYs) are
implemented using accurate timing when vari ous signals, such as clock, command …
implemented using accurate timing when vari ous signals, such as clock, command …