Flip-flop is one of the essential elements of data path structure design in the digital era. In
this paper, the peculiar Flip-flop topologies, called as Conditional Pass Logic Static D-Flip …

Although we may be at the end of Moore's law, lowering chip power consumption is still the
primary driving force for the designers. To enable low-power operation, we propose a …

We propose a new hybrid clock distribution scheme that uses global current-mode and local
voltage-mode (VM) clocking to distribute a high-performance clock signal with reduced …

Recent digital applications will require highly efficient and high-speed gadgets and it is
related to the minimum delay and power consumption. The proposed work deals with a low …

In a high-performance VLSI design, the clock network consumes a significant amount of
power. While most existing methodologies use voltage-mode (VM) signaling, these clock …

In this paper, we present a differential current-mode pulsed flip-flop (DCMPFF) for low-power
clock distribution using a representative 45nm CMOS technology. Experimental results show …

Presently, leakage in a complementary metal oxide semiconductor (CMOS) increases due to
high static power dissipation during reading and writing operations. Spin transfer torque …

In real-time circuits, contention is a common occurrence that is overlooked in theoretical
design situations. In this study, a master-slave D flip-flop design with deliberate contention is …

Shift registers are the essential elements that are capable of storing and transmitting the
data in sequential mode in digital circuits. It consists of D flip-flops, which are connected in a …

Emerging trend in neuromorphic implementation moves towards large-scale neuron array
that processes large amount of input data. It presents a grand challenge in communication …