[图书][B] FinFET devices for VLSI circuits and systems
SK Saha - 2020 - taylorfrancis.com
To surmount the continuous scaling challenges of MOSFET devices, FinFETs have emerged
as the real alternative for use as the next generation device for IC fabrication technology …
as the real alternative for use as the next generation device for IC fabrication technology …
3-d monolithic stacking of complementary-fet on cmos for next generation compute-in-memory sram
Monolithic 3D stacking of complementary FET (CFET) SRAM arrays increases integration
density multi-fold while supporting the inherent SRAM advantages of low write power and …
density multi-fold while supporting the inherent SRAM advantages of low write power and …
Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations
Logic Built-In Self-Test (LBIST) with stored deterministic patterns is supported by the major
CAD vendors and is gaining increasing attention, especially for safety-critical applications …
CAD vendors and is gaining increasing attention, especially for safety-critical applications …
Modeling of FinFET parasitic source/drain resistance with polygonal epitaxy
In this paper, we introduce a new compact model of the parasitic resistance of a FinFET with
a hexagonal-shaped raised source-drain (S/D) structure. In contrast to previous models that …
a hexagonal-shaped raised source-drain (S/D) structure. In contrast to previous models that …
Improved compact model extraction of statistical variability in 5 nm nanosheet transistors and applied to SRAM simulations
R Li, H Luo, Y Wang, Z Yuan, A Asenov… - Semiconductor …, 2022 - iopscience.iop.org
In this paper, we look at how artificial neural networks (ANNs) may be used to improve
compact model extraction of statistical variability in 5 nm nanosheet transistors (NSTs) and …
compact model extraction of statistical variability in 5 nm nanosheet transistors (NSTs) and …
Modeling static noise margin for finfet based sram pufs
In this paper, we develop an analytical PUF model based on a compact FinFET transistor
model that calculates the PUF stability (ie PUF static noise margin (PSNM)) for FinFET …
model that calculates the PUF stability (ie PUF static noise margin (PSNM)) for FinFET …
Analog/mixed-signal design in FinFET technologies
Consumer demand for low-power mobile ICs has propelled CMOS scaling to arrive at the
fully depleted finFET with foundry offerings already available at 16/14, 10, and 7 nm. The …
fully depleted finFET with foundry offerings already available at 16/14, 10, and 7 nm. The …
Smoothing globally continuous piecewise functions based on limiting functions for device compact modeling
K Xia - Journal of Computational Electronics, 2019 - Springer
This paper generalizes a smoothing method for globally continuous piecewise functions
based on limiting functions, with and without considering symmetry. The resulting function is …
based on limiting functions, with and without considering symmetry. The resulting function is …
Vmin Testing under Variations: Defect vs. Fault Coverage
It has been known and explored for many years that low voltage testing amplifies the effect
of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning …
of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning …
[HTML][HTML] Optimization of self-heating driven leakage current properties of gate-all-around field-effect transistors using neural network modeling and genetic algorithm
C Park, I Yun - Electronics, 2021 - mdpi.com
As the technology nodes of semiconductor devices have become finer and more complex,
progressive scaling down has been implemented to achieve higher densities for electronic …
progressive scaling down has been implemented to achieve higher densities for electronic …