A 28-nm 75-fsrms Analog Fractional- Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle …

W Wu, CW Yao, K Godbole, R Ni… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
An analog fractional-sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …

A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

W Wu, CW Yao, C Guo, PY Chiang… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional-phase-locked
loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture. To …

A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking

A Santiccioli, M Mercandelli, L Bertulessi… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …

A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter

M Mercandelli, A Santiccioli, A Parisi… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …

Recent advances in high-performance frequency synthesizer design

S Levantino - 2022 IEEE Custom Integrated Circuits …, 2022 - ieeexplore.ieee.org
Whether employed as local oscillators in wireless communications or radar systems, or as
clock generators in data converters, high-performance frequency synthesizers are essential …

A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs

D Turker, A Bekele, P Upadhyaya… - … Solid-State Circuits …, 2018 - ieeexplore.ieee.org
Direct-RF data converters [1, 2] have seen increased adoption in remote-radio-head TX and
RX, due to their unparalleled bandwidth and flexibility. However, since these converters …

A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH -TDC for Low In-Band Phase Noise

Y Wu, M Shahmohammadi, Y Chen… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth
all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC) …

A 2.4-GHz reference-sampling phase-locked loop that simultaneously achieves low-noise and low-spur performance

J Sharma, H Krishnaswamy - IEEE Journal of Solid-State …, 2019 - ieeexplore.ieee.org
Dividerless synthesizers such as sub-sampling phase-locked loops (PLLs) and injection-
locked clock multipliers have demonstrated some of the lowest jitters for a given power …

A 28-nm FD-SOI 115-fs jitter PLL-based LO system for 24–30-GHz sliding-IF 5G transceivers

S Ek, T Påhlsson, C Elgaard, A Carlsson… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-
antenna transceivers is presented. The system is modular with one phase locked loop (PLL) …

Low-jitter frequency generation techniques for 5G communication: A tutorial

W Wu - IEEE Solid-State Circuits Magazine, 2021 - ieeexplore.ieee.org
5G is the latest global wireless standard, known as the fifth generation of cellular mobile
communication technology. Compared to 4G LTE, 5G increases peak data rates and …