Arbitrating among portions of multiple transactions and transmitting a winning portion over
one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by …

A controller for a shared memory is disclosed. The controller comprises a transaction
scanner configured to scan-in a plurality of transactions to access the shared memory and to …

Embodiments can provide additional computing resources at minimal and incremental cost
by providing instances of one or more server compute subsystems on a system-on-chip. The …

In an approach for managing a set of tests to run on a set of platforms, a processor identifies
a set of tests to run on a set of platforms and one or more priorities associated with the set of …

Apparatus, methods, and computer-readable storage media are disclosed for core-to-core
communication between physical and/or virtual processor cores. In some examples of the …

A system for consistently implementing reset and power management of IP agents on a
System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes …

Embodiments of the technology can provide the flexibility of fine-grained dynamic
partitioning of various compute resources among different compute subsystems on an SoC …

Arbitrating among portions of multiple transactions and transmitting a winning portion over
one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by …

(57) ABSTRACT A memory controller that implements an interleaving and arbitration
scheme includes an address decoder that selects a memory bank for an access request …

Embodiments of the technology can provide steering of one or more I/O resources to
compute subsystems on a system-on chip (SoC). The SoC may include a first I/O subsystem …