Aspects of the present disclosure relate to a method and system for hybrid and/or distributed
implementation of generation and/or execution of power profile management instructions …

Example implementations described herein are directed to a configurable building block,
such as a router, for implementation of a Network on Chip (NoC). The router is …

US9158882B2 - Automatic pipelining of NoC channels to meet timing and/or performance -
Google Patents US9158882B2 - Automatic pipelining of NoC channels to meet timing and/or …

Aspects of the present disclosure are directed to a power specification and Network on Chip
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …

Aspects of the present disclosure are directed to methods, systems, and non-transitory
computer readable mediums for selective visualization and performance characterization of …

Example implementations described herein are directed to a micro-architecture of NoC
router clocking which allows for a flexible Globally Asynchronous Locally Synchronous …

Example implementations are directed to more efficiently delivering a multicast message to
multiple destination components from a source component. Multicast environment is …

Referring to FIG. 1, an embodiment of a block diagram for a computing system including a
multicore processor is depicted. Processor 100 includes any processor or process ing …

Abstract Systems and methods for performing multi-message transaction based
performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect …

The present disclosure is directed to system-on-chip (SoC) optimization through
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …