Design and implementation of 16× 16 multiplier using Vedic mathematics
SP Pohokar, RS Sisal, KM Gaikwad… - … and Control (ICIC), 2015 - ieeexplore.ieee.org
This paper briefly describes the Urdhva-Tiryagbhyam Sutra of vedic mathematics and we
have designed multiplier based on the sutra. Vedic Mathematics is the ancient system of …
have designed multiplier based on the sutra. Vedic Mathematics is the ancient system of …
Design of speed, energy and power efficient reversible logic based vedic ALU for digital processors
A Gupta, U Malviya, V Kapse - 2012 Nirma University …, 2012 - ieeexplore.ieee.org
Now days most of the circuits which are going to be designed to perform any specific or
safety critical operations are mainly based upon the digital domain, where microprocessors …
safety critical operations are mainly based upon the digital domain, where microprocessors …
[PDF][PDF] Implementation and analysis of power, area and delay of array, Urdhva, Nikhilam Vedic multipliers
CH Kumar - International Journal of Scientific and Research …, 2013 - Citeseer
The performance of the any processor will depend upon its power and delay. The power and
delay should be less in order to get a effective processor. In processors the most commonly …
delay should be less in order to get a effective processor. In processors the most commonly …
Vedic multiplier implementation in VLSI
MK Sona, V Somasundaram - Materials Today: Proceedings, 2020 - Elsevier
In processors the complex and challenging operations are needed to be handled to
overcome the demands, which leads to an increase in processor cores. This leads to an …
overcome the demands, which leads to an increase in processor cores. This leads to an …
Publishing historical texts on the semantic web-a case study
E Ahonen, E Hyvonen - 2009 IEEE International Conference on …, 2009 - ieeexplore.ieee.org
Historical texts are an important component of cultural heritage, and are being digitized and
published on the web in various portals for the researchers and the public. However …
published on the web in various portals for the researchers and the public. However …
[PDF][PDF] Implementation of power efficient vedic multiplier
N Kayalvizhi, A Sree Nivas - International Journal of Computer …, 2012 - Citeseer
Vedic multiplier is based on the ancient algorithms (sutras) followed in INDIA for
multiplication. This work is based on one of the sutras called “Nikhilam Sutra”. These sutras …
multiplication. This work is based on one of the sutras called “Nikhilam Sutra”. These sutras …
Performance analysis for Vedic multiplier using modified full adders
VL Bandi - 2017 Innovations in Power and Advanced …, 2017 - ieeexplore.ieee.org
Area efficient architecture is today's major concern in the field of VLSI, Digital signal
processing circuits, cryptographic algorithms, wireless communications and Internet of …
processing circuits, cryptographic algorithms, wireless communications and Internet of …
LVCMOS based thermal aware energy efficient vedic multiplier design on FPGA
K Goswami, B Pandey - 2014 International Conference on …, 2014 - ieeexplore.ieee.org
In this work, we are integrating thermal aware design approach in energy efficient Vedic
multiplier on FPGA. In the beginning of this universe, Veda describes heat receiving from the …
multiplier on FPGA. In the beginning of this universe, Veda describes heat receiving from the …
Different I/O standard and technology based thermal aware energy efficient Vedic multiplier design for green wireless communication on FPGA
This paper deals with low power multiplier design that plays a significant role in green
wireless communications systems. Over the period of time, researchers have proposed …
wireless communications systems. Over the period of time, researchers have proposed …
[PDF][PDF] Vedic mathematics for digital signal processing operations: a review
KM Gaikwad, MS Chavan - International Journal of Computer …, 2015 - researchgate.net
Speed improvement in Digital signal processing is considered to be challenging. High
speed multipliers and adders are prime requirement for digital filters and for FFT operations …
speed multipliers and adders are prime requirement for digital filters and for FFT operations …