Semiconductor multilayer nanometrology with machine learning

H Kwak, J Kim - Nanomanufacturing and Metrology, 2023 - Springer
We review the measurement methods and thickness characterization algorithms of
semiconductor multilayer devices. Today's ultrahigh-density, high-energy-efficient three …

Simulation and performance analysis of dielectric modulated dual source trench gate TFET biosensor

C Chong, H Liu, S Wang, S Chen - Nanoscale Research Letters, 2021 - Springer
In this paper, a dielectric modulated double source trench gate tunnel FET (DM-DSTGTFET)
based on biosensor is proposed for the detection of biomolecules. DM-DSTGTFET adopts …

Prospective sensing applications of novel heteromaterial based dopingless nanowire-TFET at low operating voltage

N Kumar, A Raman - IEEE Transactions on Nanotechnology, 2020 - ieeexplore.ieee.org
Most of the sensors are based on different device architectures depending on the
application type. A novel dopingless (DL) vertical Nanowire (VNW)-TFET is proposed that is …

A barrier controlled charge plasma-based TFET with gate engineering for ambipolar suppression and RF/linearity performance improvement

K Nigam, S Pandey, PN Kondekar… - … on Electron Devices, 2017 - ieeexplore.ieee.org
To address the fabrication complexity and cost of nanoscale devices, a dual material control
gate charge-plasma-based tunnel FET (DMCG-CPTFET) is presented for the first time for the …

Investigation of negative capacitance gate-all-around tunnel FETs combining numerical simulation and analytical modeling

C Jiang, R Liang, J Xu - IEEE Transactions on Nanotechnology, 2016 - ieeexplore.ieee.org
A short-channel negative capacitance gate-all-around tunnel field-effect transistor (NC-GAA-
TFET) with a ferroelectric gate stack is proposed. Device performance is investigated by …

Reduction of TFET OFF-current and subthreshold swing by lightly doped drain

J Wu, Y Taur - IEEE Transactions on Electron Devices, 2016 - ieeexplore.ieee.org
This brief models the effect of lightly doped drain on the I ds-V gs and I ds-V ds
characteristics of tunnel FETs. It is shown that an extended drain depletion region can …

Vertically integrated multiple nanowire field effect transistor

BH Lee, MH Kang, DC Ahn, JY Park, T Bang… - Nano Letters, 2015 - ACS Publications
A vertically integrated multiple channel-based field-effect transistor (FET) with the highest
number of nanowires reported ever is demonstrated on a bulk silicon substrate without use …

Negative capacitance gate-all-around tunnel FETs for highly sensitive label-free biosensors

FI Sakib, MA Hasan, M Hossain - IEEE Transactions on Electron …, 2021 - ieeexplore.ieee.org
We propose a nanoscale, highly sensitive and label-free biosensor based on negative
capacitance gate-all-around tunnel field-effect transistor (NC-GAA-TFET). NC-GAA-TFETs …

Analytical surface potential and drain current models of dual-metal-gate double-gate tunnel-FETs

V Prabhat, AK Dutta - IEEE Transactions on Electron Devices, 2016 - ieeexplore.ieee.org
In this paper, a new 2-D analytical model for the surface potential of a dual-metal-gate
double-gate tunnel field-effect transistor is presented. It takes into account the effects of the …

Influence of threshold voltage performance analysis on dual halo gate stacked triple material dual gate TFET for ultra low power applications

M Venkatesh, NB Balamurugan - Silicon, 2021 - Springer
In this article, a two dimensional (2-D) threshold voltage modeling based gate and channel
engineering are developed analytically for Dual Halo Gate Stacked Triple Material Dual …