Reliability-aware system synthesis
M Glaß, M Lukasiewycz, T Streichert… - … , Automation & Test …, 2007 - ieeexplore.ieee.org
Increasing reliability is one of the most important design goals for current and future
embedded systems. In this paper, we will put focus on the design phase in which reliability …
embedded systems. In this paper, we will put focus on the design phase in which reliability …
Simulation-based method for synthesizing soft error tolerant combinational circuits
AH El-Maleh, KAK Daud - IEEE Transactions on Reliability, 2015 - ieeexplore.ieee.org
Due to current technology scaling trends, digital designs are becoming more sensitive to
radiation-induced particle hits resulting from radioactivity decay and cosmic rays. A low …
radiation-induced particle hits resulting from radioactivity decay and cosmic rays. A low …
Integer linear programming-based optimization methodology for reliability and energy-aware high-level synthesis
Continuous decrease in the transistor technology sizes has enabled much denser
packaging of electronic components on chips, which has resulted in integrated circuits with …
packaging of electronic components on chips, which has resulted in integrated circuits with …
High-level synthesis for multi-cycle transient fault tolerant datapaths
T Inoue, H Henmi, Y Yoshikawa… - 2011 IEEE 17th …, 2011 - ieeexplore.ieee.org
As the advance in semiconductor technology, the tolerance for transient faults caused by
particle strike, called SET (single event transient), becomes an important issue, and …
particle strike, called SET (single event transient), becomes an important issue, and …
Incorporating graceful degradation into embedded system design
In this work, the focus is put on the behavior of a system in case a fault occurs that disables
the system from executing its applications. Instead of executing a random subset of the …
the system from executing its applications. Instead of executing a random subset of the …
Design space exploration of reliable networked embedded systems
In this paper, a new methodology is presented for topology optimization of networked
embedded systems as they occur in automotive and avionic systems as well as wireless …
embedded systems as they occur in automotive and avionic systems as well as wireless …
Symbolic reliability analysis and optimization of ECU networks
Increasing reliability at a minimum amount of extra cost is a major challenge in todays ECU
network design. Considering reliability as an objective already in early design phases has …
network design. Considering reliability as an objective already in early design phases has …
[HTML][HTML] Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications
SRAM-based FPGAs are increasingly popular in the aerospace industry due to their field
programmability and low cost. However, they suffer from cosmic radiation induced Single …
programmability and low cost. However, they suffer from cosmic radiation induced Single …
Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis
AA Koufopoulou, K Xevgeni… - 2022 IEEE 28th …, 2022 - ieeexplore.ieee.org
As the complexity of digital circuits increases, High-Level Synthesis (HLS) is becoming a
valuable tool to increase productivity and design reuse by utilizing relevant Electronic …
valuable tool to increase productivity and design reuse by utilizing relevant Electronic …
A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications
Space computing systems commonly use field-programmable gate arrays to provide fault
tolerance by applying triple modular redundancy (TMR) to existing register-transfer-level …
tolerance by applying triple modular redundancy (TMR) to existing register-transfer-level …