Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units
(ALUs) of modern computing systems. Recently, there have been massive research interests …

This paper presents a low voltage and high performance 1-bit full adder designed with an
efficient internal logic structure that leads to have a reduced Power Delay Product (PDP) …

An energy efficient internal logic approach for designing two 1-bit full adder cells is
proposed in this work. It is based on decomposition of the full adder logic into the smaller …

In the complex computing system, processing units are dealing with devices of smaller size,
which are sensitive to the transient faults. A transient fault occurs in a circuit caused by the …

A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP)
in the presented full adder cell. A new method is used in order to design a full‐swing full …

This paper presents a new 8-bit adder circuit, called discrepant low PDP 8-bit adder (DLPA)
based on three new full adder cells, which have been designed based on requirements of …

Combination of high-mean free path and scaling ability makes graphene nanoribbon (GNR)
attractive for application of field-effect transistors and subject of intense research. Here, we …

Length of saturation region (LVSR) as an important parameter in nanoscale devices, which
controls the drain breakdown voltage is in our focus. This paper presents three models for …

Adders are widely used in many digital circuits and play an integral role in the
implementation of various logic circuits. From the starting days, efforts are being made to …

Abstract A novel 13-transistor, low-power true single-phase clocked (TSPC) flip-flop design
is proposed which improves clock loading, power consumption, and performance. The …