During the manufacturing test process, researchers often overlook those latent defects
(induce failure) which, similar to process variation (PV, will not induce fatal failure in early life …

FinFET technology has become an attractive candidate for high-performance and power-
efficient applications. In the other hand, the behavior of FinFET devices is influenced by self …

This article proposes an electrical analysis of a new defect mechanism, to be named as b-
open defect, which may occur in nanometer technologies due to the use of the Self-Aligned …

Staggered Redundant execution (SRE) is a fault-tolerance mechanism that has been widely
deployed in the context of safety-critical applications. SRE not only protects the system in the …

This paper proposes a low-cost yet high-coverage design-for-testability (DFT) scheme for
improving the detection of hard-to-detect (HtD) faults in STT-MRAMs. It is based on …

FinFET technology is used in leading high-performance/power-efficient electronic products.
This technology has proven its efficiency after 22nm technology nodes. However, FinFET …

This paper proposes a design-for-testability (DFT) scheme and a test method to improve the
detection of hard-to-detect (HtD) faults of STT-MRAMs. The proposed DFT scheme …

To improve the test accuracy and fault coverage of high-speed railway-related equipment
boards, a time-varying pseudorandom disturbance algorithm based on the automatic test …

High-quality memory diagnosis methodologies are critical enablers for scaled memory
devices as they reduce time to market and provide valuable information regarding test …

Abstract Limitations on Complementary Metal Oxide Semiconductor (CMOS) technology
scaling combined with the increasing demand for emerging applications requiring high …