Circuit-level impact of a-Si: H thin-film-transistor degradation effects

DR Allee, LT Clark, BD Vogt… - … on Electron Devices, 2009 - ieeexplore.ieee.org
This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical
stress, examining the implications for various types of circuitry. Experimental measurements …

[图书][B] Modelling of interface carrier transport for device simulation

D Schroeder - 1994 - books.google.com
1 Introduction.-2 Charge Transport in the Volume.-3 General Electronic Model of the
Interface.-4 Charge Transport Across the Interface.-5 Semiconductor-Insulator Interface.-6 …

A physics-based approach to model hot-electron trapping kinetics in p-GaN HEMTs

N Modolo, C De Santi, A Minetto… - IEEE Electron …, 2021 - ieeexplore.ieee.org
Hot electron trapping can significantly modify the performance of GaN-based HEMTs during
hard switching operation. In this letter, we present a physics-based model based on rate …

The impact of hot electrons and self-heating during hard-switching in AlGaN/GaN HEMTs

F Yang, S Dalcanale, M Gajda… - … on Electron Devices, 2020 - ieeexplore.ieee.org
In this article, we investigate the impact of hard-switching on the dynamic ON-resistance
(RON) in the AlGaN/GaN high-electron mobility transistors (HEMTs). The pulsed …

Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation

Y Leblebici, SM Kang - … on computer-aided design of integrated …, 1992 - ieeexplore.ieee.org
The authors present an accurate one-dimensional device model for the simulation of nMOS
transistors with hot-carrier-induced oxide damage. The model uses a realistic charge density …

Localization of gate bias induced threshold voltage degradation in a-Si: H TFTs

R Shringarpure, S Venugopal, LT Clark… - IEEE Electron …, 2007 - ieeexplore.ieee.org
This letter describes a method to identify the channel region of hydrogenated amorphous
silicon thin film transistors (a-Si: H TFTs) in which threshold voltage (V th) degradation …

A physical-based analytical model for hot-carrier induced saturation current degradation of p-MOSFET's

Y Pan - IEEE transactions on electron devices, 1994 - ieeexplore.ieee.org
The delay time of a CMOS inverter is directly related to the p-MOSFET saturation current. An
accurate aging model for the saturation current is essential for the modeling of the CMOS …

A new self-consistent modeling approach to investigating MOSFET degradation

W Hansch, AV Schwerin… - IEEE electron device …, 1990 - ieeexplore.ieee.org
A modeling tool is presented that allows a complete analysis of a DC stress experiment
without assuming the location and amount of trapped oxide charges and interface states. To …

A coupled study by floating-gate and charge-pumping techniques of hot carrier-induced defects in submicrometer LDD n-MOSFET's

D Vuillaume, JC Marchetaux… - IEEE transactions on …, 1993 - ieeexplore.ieee.org
The creation of defects by hot-carrier effect in submicrometer (0.85-mu m) LDD n-MOSFETs
is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that …

Underlying physics and effects of silicon APD aging in automotive LiDAR applications

S Kammer - 2022 - ul.qucosa.de
Abstract (EN) Over 90% of traffic accidents are caused by human error. Therefore, the
realization of autonomous driving could save countless lives and drastically reduce the …