Design and evaluation of radiation-hardened standard cell flip-flops
O Schrape, M Andjelković… - … on Circuits and …, 2021 - ieeexplore.ieee.org
Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-
effective solution for space applications. In this paper we demonstrate how a standard non …
effective solution for space applications. In this paper we demonstrate how a standard non …
A quatro-based 65-nm flip-flop circuit for soft-error resilience
A flip-flop circuit hardened against soft errors is presented in this paper. This design is an
improved version of Quatro for further enhanced soft-error resilience by integrating the guard …
improved version of Quatro for further enhanced soft-error resilience by integrating the guard …
Is backside the new backdoor in modern socs?
N Vashistha, MT Rahman… - 2019 IEEE …, 2019 - ieeexplore.ieee.org
Modern integrated circuits (ICs) possess several countermeasures to safeguard sensitive
data and information stored in the device. In recent years, semi-invasive physical attacks …
data and information stored in the device. In recent years, semi-invasive physical attacks …
Ring oscillator under laser: potential of pll-based countermeasure against laser fault injection
As a typical semi-invasive attack against cryptographic primitives, laser fault injection (LFI)
has emerged as a serious threat for security ICs. However, very few countermeasures …
has emerged as a serious threat for security ICs. However, very few countermeasures …
Technology scaling comparison of flip-flop heavy-ion single-event upset cross sections
NJ Gaspard, S Jagannathan, ZJ Diggins… - … on Nuclear Science, 2013 - ieeexplore.ieee.org
Heavy-ion experimental results from flip-flops in 180-nm to 28-nm bulk technologies are
used to quantify single-event upset trends. The results show that as technologies scale, D …
used to quantify single-event upset trends. The results show that as technologies scale, D …
An SEU-tolerant DICE latch design with feedback transistors
This paper presents an SEU-tolerant Dual Interlocked Storage Cell (DICE) latch design with
both PMOS and NMOS transistors in the feedback paths. The feedback transistors improve …
both PMOS and NMOS transistors in the feedback paths. The feedback transistors improve …
Supply voltage dependence of heavy ion induced SEEs on 65 nm CMOS bulk SRAMs
Soft Error Rates (SER) of hardened and unhardened SRAM cells need to be experimentally
characterized to determine their appropriate applications in radiation environments. This …
characterized to determine their appropriate applications in radiation environments. This …
Performance, metastability, and soft-error robustness trade-offs for flip-flops in 40 nm CMOS
In modern CMOS processes, soft errors and metastability are two prominent failure
mechanisms. Radiation induced single event upsets, or soft-errors, have become a …
mechanisms. Radiation induced single event upsets, or soft-errors, have become a …
[PDF][PDF] A review paper on design of positive edge triggered D flip-flop using VLSI technology
PG Dhoble, AD Kale - International Journal of Engineering Research …, 2014 - academia.edu
A Delay (D) flip-flop is an edge triggering device. A high speed, low power consumption,
positive edge triggered Delay (D) flip-flop can be designed for increasing the speed of …
positive edge triggered Delay (D) flip-flop can be designed for increasing the speed of …
An area efficient stacked latch design tolerant to SEU in 28 nm FDSOI technology
In this paper, we present D flip-flop, Quatro, and stacked Quarto flip-flop designs fabricated
in a commercial 28-nm CMOS FDSOI technology. Stacked-transistor structures are …
in a commercial 28-nm CMOS FDSOI technology. Stacked-transistor structures are …