Understanding algebraic rewriting for arithmetic circuit verification: a bit-flow model

M Ciesielski, T Su, A Yasin, C Yu - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
This paper addresses theoretical aspects of arithmetic circuit verification based on algebraic
rewriting. Its goal is to advance the understanding of algebraic techniques for arithmetic …

Formal verification of arithmetic circuits by function extraction

C Yu, W Brown, D Liu, A Rossi… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This paper presents an algebraic approach to functional verification of gate-level, integer
arithmetic circuits. It is based on extracting a unique bit-level polynomial function computed …

Automated test generation for debugging multiple bugs in arithmetic circuits

F Farahmandi, P Mishra - IEEE Transactions on Computers, 2018 - ieeexplore.ieee.org
Optimized and custom arithmetic circuits are widely used in embedded systems such as
multimedia applications, cryptography systems, signal processing and console games …

Automated test generation for debugging arithmetic circuits

F Farahmandi, P Mishra - 2016 Design, Automation & Test in …, 2016 - ieeexplore.ieee.org
Optimized and custom arithmetic circuits are widely used in embedded systems such as
multimedia applications, cryptography systems, signal processing and console games …

Automated debugging of arithmetic circuits using incremental gröbner basis reduction

F Farahmandi, P Mishra - 2017 IEEE International Conference …, 2017 - ieeexplore.ieee.org
Symbolic algebra is a promising approach to verify large and complex arithmetic circuits.
Existing algebraic-based verification methods generate a remainder to indicate buggy …

Approximate hardware generation using symbolic computer algebra employing grobner basis

S Froehlich, D Große… - 2018 Design, Automation & …, 2018 - ieeexplore.ieee.org
Many applications are inherently error tolerant. Approximate Computing is an emerging
design paradigm, which gives the opportunity to make use of this error tolerance, by trading …

Debugging circuit for detecting timing errors in serializer for high-speed wireline interfaces

J Lee, JH Chae - IEEE Access, 2024 - ieeexplore.ieee.org
Several circuit components can induce bit errors at high-speed wireline interfaces. Hence,
accurate identification and correction of error points in various circuits using straightforward …

Combining symbolic computer algebra and boolean satisfiability for automatic debugging and fixing of complex multipliers

A Mahzoon, D Große… - 2018 IEEE Computer …, 2018 - ieeexplore.ieee.org
If verification of a digital circuit fails, then debugging and fixing become the major
subsequent tasks. Arithmetic units are among the most challenging circuits for debugging …

Polynomial Formal Verification of Arithmetic Circuits

A Mahzoon, R Drechsler - Foundations and Trends® in …, 2024 - nowpublishers.com
In recent years, significant effort has been put into developing formal verification approaches
by both academic and industrial research. In practice, these techniques often give satisfying …

Efficient parallel verification of galois field multipliers

C Yu, M Ciesielski - 2017 22nd Asia and South Pacific Design …, 2017 - ieeexplore.ieee.org
Galois field (GF) arithmetic is used to implement critical arithmetic components in
communication and security-related hardware, and verification of such components is of …