Towards practical lattice-based public-key encryption on reconfigurable hardware

T Pöppelmann, T Güneysu - Selected Areas in Cryptography--SAC 2013 …, 2014 - Springer
With this work we provide further evidence that lattice-based cryptography is a promising
and efficient alternative to secure embedded applications. So far it is known for solid security …

Enhanced lattice-based signatures on reconfigurable hardware

T Pöppelmann, L Ducas, T Güneysu - Cryptographic Hardware and …, 2014 - Springer
Abstract The recent Bimodal Lattice Signature Scheme (Bliss) showed that lattice-based
constructions have evolved to practical alternatives to RSA or ECC. Besides reasonably …

Gaussian random number generation: A survey on hardware architectures

JS Malik, A Hemani - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
Some excellent surveys of the Gaussian random number generators (GRNGs) from the
algorithmic perspective exist in the published literature to date (eg, Thomas et al.[2007]). In …

Reduced-complexity min-sum algorithm for decoding LDPC codes with low error-floor

F Angarita, J Valls, V Almenar… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
This paper proposes a low-complexity min-sum algorithm for decoding low-density parity-
check codes. It is an improved version of the single-minimum algorithm where the two …

Dinar: Enabling distribution agnostic noise injection in machine learning hardware

K Ganesan, V Karyofyllis, J Attai, A Hamoda… - Proceedings of the 12th …, 2023 - dl.acm.org
Machine learning (ML) has seen a major rise in popularity on edge devices in recent years,
ranging from IoT devices to self-driving cars. Security in a critical consideration on these …

An Efficient FPGA-Based Gaussian Random Number Generator Using an Accurate Segmented Box–Muller Method

S Dahmani, M Maamoun, G Zerari, N Chabini… - IEEE …, 2023 - ieeexplore.ieee.org
In this paper, we introduce an accurate, efficient, and optimized design and implementation
of a Gaussian pseudo random number generator (PRNG) on a field-programmable gate …

Towards FPGA emulation of fiber-optic channels for deep-BER evaluation of DSP implementations

E Börjeson, C Fougstedt… - Signal Processing in …, 2019 - opg.optica.org
Towards FPGA Emulation of Fiber-Optic Channels for Deep-BER Evaluation of DSP
Implementations Page 1 SpTh1E.4.pdf Advanced Photonics Congress (IPR, Networks, NOMA …

Cycle-slip rate analysis of blind phase search DSP circuit implementations

E Börjeson, P Larsson-Edefors - 2020 Optical Fiber …, 2020 - ieeexplore.ieee.org
Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit Implementations Page 1 M4J.3.pdf
OFC 2020 © OSA 2020 Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit …

Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance

Z Chen, K Song, D Zou, C Zhu… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
With the increasing speed and more stringent Bit Error Rate (BER) requirements of serial
wireline links, FPGA-based SerDes (serializer/deserializer) simulation systems have gained …

High-speed discrete Gaussian sampler with heterodyne chaotic laser inputs

Y Liu, XZ Li, RCC Cheung, SC Chan… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Considering the limited throughput of a true random number generator (TRNG), the time
independence of speed in a real discrete Gaussian sampler design was usually sacrificed …