A redundancy eliminated flip-flop (REFF) is proposed targeting wide-range voltage
scalability (1–0.3 V). Two types of redundancies are eliminated in the REFF to achieve low …

A static contention-free differential flip-flop (SCDFF) is presented in 28-nm CMOS for low-
voltage and low-power applications. The SCDFF offers fully static and contention-free …

Power-performance constraints have been the key driving force that motivated the
microprocessor industry to bring unique design techniques in the past two decades. The …

This paper proposes a novel design for a master-slave flip-flop that utilizes a hybrid topology
and a single-phase clock, consisting of 18 transistors. Proposed Flip-Flop Circuit (PFC) is …

As the demand for high-performance microprocessors increases, the circuit complexity and
the rate of data transfer increases resulting in higher power consumption. We propose a …

A redundancy eliminated flip-flop (REFF) is presented in 28-nm LP process, targeting wide-
range voltage scalability (1-0.3 V). The REFF removes redundant clock transitions to reduce …

Along with size and performance considerations, power consumption is regarded as a
significant challenge in current VLSI design. In digital systems, the flip flop is an extremely …

Flip-flops with ultra-wide-range dynamic voltage scaling capability are attractive for ultra-low
power applications. In this paper, a single-phase split-controlled flip-flop (SCFF) is proposed …

The D-flip-flop functions as an electronic memory unit due to its ability to maintain a
consistent output unless intentionally modified by adjusting the state of the D input and …

In real-time circuits, contention is a common occurrence that is overlooked in theoretical
design situations. In this study, a master-slave D flip-flop design with deliberate contention is …